Direct multi-level cell programming

• US 8,995,194 B2
• Filed: 10/08/2014
• Issued: 03/31/2015
• Est. Priority Date: 08/29/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Marcu, Alon, Sharon, Eran, Alrod, Idan, Li, Yan, Oshinsky, Hadas
• Primary Examiner(s): Lappas, Jason
• Application Number:
  US14/509,602
• Publication Number:
  US 20150023099A1
• Time in Patent Office: 174 Days
• Field of Search: 365/185.17, 365/185.33, 365/185.28
• US Class Current: 365/185.17
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5643 Multilevel memory comprising cache storage devices

Abstract

A method is performed in a data storage device that includes a controller coupled to a non-volatile memory. The non-volatile memory includes a group of storage elements. Each storage element is configured to store multiple data bits. Data is sent from the controller to the non-volatile memory and first bits corresponding to a first portion of the data are stored into the group of storage elements during a first write stage. Each storage element of the group of storage elements stores at least one bit of the first bits upon completion of the first write stage. Second bits corresponding to a second portion of the data are sent to a second memory without sending the first bits to the second memory. The second bits are retrieved from the second memory and at least the second bits are stored into the group of storage elements during a second write stage.

Claims

1. A data storage device comprising:

a non-volatile memory including a group of storage elements;

a set of latches configured to store data to be programmed to the group of storage elements during each particular stage of a multi-stage write operation; and

a second memory configured to store bits corresponding to one or more portions of the data during a time period between stages of the multi-stage write operation,

wherein the second memory is configured to receive the bits corresponding to the one or more portions of the data from the latches without receiving bits corresponding to a first portion of the data that is programmed to the group of storage elements during a first stage of the multi-stage write operation, and

wherein the latches are configured to receive the bits corresponding to the one or more portions of the data from the second memory and to receive the bits corresponding to the first portion of the data from the group of storage elements during a subsequent stage of the multi-stage write operation.

2. The data storage device of claim 1, further comprising mapping circuitry coupled to the latches, wherein the mapping circuitry is configured to modify the data in the latches prior to the first stage, from a grey-type encoding to a binary-type encoding.

3. The data storage device of claim 2, wherein the mapping circuitry includes an exclusive-OR circuit to generate at least one value of the binary-type encoding of the data based on values of the grey-type encoding of the data.

4. The data storage device of claim 2, wherein the mapping circuitry is configured to perform a table lookup operation to determine at least one value of the binary-type encoding of the data based on values of the grey-type encoding of the data.

5. The data storage device of claim 1, wherein the second memory includes a single level cell (SLC) cache.

6. The data storage device of claim 1, further comprising a controller, the controller configured to send the data to the non-volatile memory to be stored at the group of storage elements.

7. The data storage device of claim 6, further comprising a third memory configured to store one or more portions of the data.

8. The data storage device of claim 7, wherein the third memory includes a single level cell (SLC) cache.

9. The data storage device of claim 7, wherein the third memory is within the controller.

10. The data storage device of claim 7, wherein the third memory is within the non-volatile memory.

11. An apparatus comprising:

a non-volatile memory including a group of storage elements;

a controller configured to send data to be programmed to the group of storage elements;

a set of latches configured to store the data during each particular stage of a multi-stage write operation; and

a second memory configured to store bits corresponding to one or more portions of the data during a time period between stages of the multi-stage write operation,

wherein the second memory is configured to receive the bits corresponding to the one or more portions of the data from the latches without receiving bits corresponding to a first portion of the data that is programmed to the group of storage elements during a first stage of the multi-stage write operation, and

wherein the latches are configured to receive the bits corresponding to the one or more portions of the data from the second memory and to receive the bits corresponding to the first portion of the data from the group of storage elements during a subsequent stage of the multi-stage write operation.

12. The apparatus of claim 11, further comprising mapping circuitry coupled to the latches, wherein the mapping circuitry is configured to modify the data in the latches, prior to the first stage, from a grey-type encoding to a binary-type encoding.

13. The apparatus of claim 12, wherein the mapping circuitry includes an exclusive-OR circuit to generate at least one value of the binary-type encoding of the data based on values of the grey-type encoding of the data.

14. The apparatus of claim 12, wherein the mapping circuitry is configured to perform a table lookup operation to determine at least one value of the binary-type encoding of the data based on values of the grey-type encoding of the data.

15. The apparatus of claim 11, wherein the second memory includes a single level cell (SLC) cache.

16. The apparatus of claim 11, further comprising a third memory configured to store one or more portions of the data.

17. The apparatus of claim 16, wherein the third memory includes a single level cell (SLC) cache.

18. The apparatus of claim 16, wherein the third memory is within the controller.

19. The apparatus of claim 16, wherein the third memory is within the non-volatile memory.