Circuit devices and methods having adjustable transistor body bias

• US 8,995,204 B2
• Filed: 06/23/2011
• Issued: 03/31/2015
• Est. Priority Date: 06/23/2011
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: SuVolta, Inc.
• Inventors: Clark, Lawrence T., McWilliams, Bruce, Rogenmoser, Robert
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US13/167,625
• Publication Number:
  US 20120327725A1
• Time in Patent Office: 1,377 Days
• Field of Search: 365/189.011, 365/189.09, 365/185.18, 365/191
• US Class Current: 365/189.011
• CPC Class Codes: G11C 11/412 using field-effect transistors only

Abstract

Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.

Claims

1. An integrated circuit (IC) device, comprising:

at least a first biased section comprising a plurality of biasable NMOS transistors and a plurality of biasable PMOS transistors;

at least one bias generation circuit configured to generate a plurality of bias voltages;

a plurality of performance values, each performance value being associated with an NMOS bias voltage and a PMOS bias voltage of the plurality of bias voltages, each performance value corresponding to a speed of the first biased section when the associated NMOS bias voltage is coupled to the biasable NMOS transistors and the associated PMOS bias voltage is coupled to the biasable PMOS transistors;

a plurality of leakage reduction coefficients, each leakage reduction coefficient being associated with an NMOS bias voltage and a PMOS bias voltage of the plurality of bias voltages, each leakage reduction coefficient corresponding to a leakage current reduction of the first biased section when the associated NMOS bias voltage is coupled to the biasable NMOS transistors and the associated PMOS bias voltage is coupled to the biasable PMOS transistors; and

at least one bias control section responsive to the plurality of performance values and the plurality of leakage reduction coefficients and adapted to selectively couple an NMOS bias voltage to the NMOS biasable transistors and a PMOS bias voltage to the PMOS biasable transistors, such that the selectively coupled NMOS and PMOS bias voltages provide a first biased section having a predetermined minimum speed and a lowest leakage current corresponding the predetermined minimum speed;

wherein

the at least one bias control section determines a plurality of candidate performance values that correspond to the first biased section having the predetermined minimum speed, the bias control section further evaluating the candidate performance values and selecting an optimal performance value having an associated leakage reduction coefficient within predetermined limits, the bias control section selectively coupling the NMOS and PMOS bias voltages associated with the optimal performance value to the first biased section.

2. The IC device of claim 1, wherein the optimal performance value is a candidate performance value having an highest associated leakage reduction coefficient.

3. The IC device of claim 1, wherein the leakage reduction coefficients correspond to measured leakage currents of at least the biasable NMOS transistors.

4. The IC device of claim 1, wherein the leakage reduction coefficients correspond to circuit simulations of a leakage current of at least the NMOS transistors.

5. The IC device of claim 1, wherein the leakage reduction coefficients correspond to measured leakage currents of at least the biasable PMOS transistors.

6. The IC device of claim 1, wherein the leakage reduction coefficients correspond to circuit simulations of a leakage current of at least the PMOS transistors.

7. An integrated circuit (IC) device, comprising:

at least a first biased section comprising a plurality of biasable NMOS transistors and a plurality of biasable PMOS transistors;

at least one bias generation circuit configured to generate a plurality of bias voltages;

a plurality of performance values, each performance value being associated with an NMOS bias voltage and a PMOS bias voltage of the plurality of bias voltages, each performance value corresponding to a speed of the first biased section when the associated NMOS bias voltage is coupled to the biasable NMOS transistors and the associated PMOS bias voltage is coupled to the biasable PMOS transistors;

a plurality of leakage reduction coefficients, each leakage reduction coefficient being associated with an NMOS bias voltage and a PMOS bias voltage of the plurality of bias voltages, each leakage reduction coefficient corresponding to a leakage current reduction of the first biased section when the associated NMOS bias voltage is coupled to the biasable NMOS transistors and the associated PMOS bias voltage is coupled to the biasable PMOS transistors;

at least one bias control section responsive to the plurality of performance values and the plurality of leakage reduction coefficients and adapted to selectively couple an NMOS bias voltage to the NMOS biasable transistors and a PMOS bias voltage to the PMOS biasable transistors, such that the selectively coupled NMOS and PMOS bias voltages provide a first biased section having a predetermined minimum speed and a lowest leakage current corresponding the predetermined minimum speed;

the leakage reduction coefficients comprise a plurality of leakage reduction tables, each leakage reduction table corresponding to a specified process skew factor; and

a skew measurement circuit to measure a die skew factor of the IC;

wherein

the bias control section selects a leakage reduction table from the plurality of leakage reduction tables based on the measured die skew factor, the bias control section being responsive to the leakage reduction coefficients of the selected leakage reduction table.

8. The IC device of claim 7, wherein the skew measurement circuit comprises a plurality of skewed ring oscillators.

9. The IC device of claim 7, wherein:

the bias control section is configured to select the leakage reduction table by interpolating between the plurality of leakage reduction tables based on the measured die skew factor.

10. The IC device of claim 7, wherein the leakage reduction table reflects a number of PMOS transistors and a number of NMOS transistors on the IC.

11. The IC device of claim 7, wherein the leakage reduction table reflects a leakage current of stacked NMOS or PMOS transistors.

12. An integrated circuit (IC) device, comprising:

at least a first biased section comprising a plurality of biasable NMOS transistors and a plurality of biasable PMOS transistors;

at least one bias generation circuit configured to generate a plurality of bias voltages;

a plurality of performance values, each performance value being associated with an NMOS bias voltage and a PMOS bias voltage of the plurality of bias voltages, each performance value corresponding to a speed of the first biased section when the associated NMOS bias voltage is coupled to the biasable NMOS transistors and the associated PMOS bias voltage is coupled to the biasable PMOS transistors;

a plurality of leakage reduction coefficients, each leakage reduction coefficient being associated with an NMOS bias voltage and a PMOS bias voltage of the plurality of bias voltages, each leakage reduction coefficient corresponding to a leakage current reduction of the first biased section when the associated NMOS bias voltage is coupled to the biasable NMOS transistors and the associated PMOS bias voltage is coupled to the biasable PMOS transistors; and

at least one bias control section responsive to the plurality of performance values and the plurality of leakage reduction coefficients and adapted to selectively couple an NMOS bias voltage to the NMOS biasable transistors and a PMOS bias voltage to the PMOS biasable transistors, such that the selectively coupled NMOS and PMOS bias voltages provide a first biased section having a predetermined minimum speed and a lowest leakage current corresponding the predetermined minimum speed, the bias control section comprising at least one emulation circuit that emulates a speed of the first biased section, the emulation circuit receiving the plurality of bias voltages and generating the plurality of performance values, each generated performance value corresponding to a NMOS bias voltage and a PMOS bias voltage selected from the plurality of bias voltages.

13. The IC device of claim 12, wherein the emulation circuit further comprises:

a plurality of ring oscillators, each comprising a plurality of stages connected in a ring, at least one of the stages including the biasable transistors, each biasable transistor being selectively coupled to a bias voltage selected from the plurality of bias voltages; and

at least one counter circuit coupled to the ring oscillators, the counter circuit generating a count value for each ring oscillator based on a frequency of the ring oscillator.

14. The IC device of claim 13, wherein:

the at least one emulation circuit further comprises a counter multiplexer (MUX) that selectively connects one of the plurality of ring oscillators to the at least one counter circuit.

15. The IC device of claim 13, wherein:

the at least one emulation circuit further comprises a counter demultiplexer (deMUX) that selectively connects the at least one counter circuit to a plurality of registers configured to store count values from the at least one counter circuit.

16. A method comprising:

receiving a plurality of performance values, each performance value being associated with an NMOS bias voltage and a PMOS bias voltage of a plurality of bias voltages, each performance value corresponding to a speed of a first biased section when the associated NMOS bias voltage is coupled to biasable NMOS transistors of the first biased section and the associated PMOS bias voltage is couples to biasable PMOS transistors of the first biased section;

receiving a plurality of leakage reduction coefficients, each leakage reduction coefficient being associated with an NMOS bias voltage and a PMOS bias voltage of the plurality of bias voltages, each leakage reduction coefficient corresponding to a leakage current of the first biased section when the associated NMOS bias voltage is coupled to biasable NMOS transistors of the first biased section and the associated PMOS bias voltage is couples to biasable PMOS transistors of the first biased section; and

selecting an NMOS bias voltage and a PMOS bias voltage to be coupled to the first biased section, such that the performance value and leakage reduction coefficient associated with the selected NMOS and PMOS bias voltage correspond to the first biased section having a predetermined minimum speed and a lowest leakage current corresponding to the predetermined minimum speed.

17. The method of claim 16, wherein selecting the NMOS bias voltage and the PMOS bias voltage to be coupled to the first biased section further comprises:

determining a plurality of candidate performance values that correspond to the first biased section having the predetermined speed;

determining an optimal performance value from the plurality of candidate performance values such that the optimal performance value has a maximum leakage reduction coefficient; and

selecting the NMOS bias voltage and the PMOS bias voltage associated with the optimal performance value as the NMOS and PMOS bias voltages to be coupled to the first biased section.

18. The method of claim 16, wherein selecting the NMOS bias voltage and the PMOS bias voltage to be coupled to the first biased section further comprises:

setting a current NMOS bias voltage to zero volts and setting a current PMOS bias voltage to a maximum bias voltage of the plurality of bias voltages;

determining a current performance value as the performance value associated with the current NMOS bias voltage and the current PMOS bias voltage;

reducing the PMOS bias voltage until the current performance value corresponds to the first biased section having the predetermined speed, if the current value associated with the current NMOS and current PMOS bias voltages does not correspond to the first bias section having the predetermined minimum speed;

determining a first leakage reduction coefficient as the leakage reduction coefficient associated with the current NMOS and the current PMOS bias voltages;

determining a second leakage reduction coefficient that is associated with a higher NMOS bias voltage, if the NMOS bias voltage is less than the maximum bias voltage of the plurality of bias voltages;

selecting the current NMOS bias voltage and the current PMOS bias voltage as the NMOS and PMOS bias voltage to be coupled to the first biased section, if the second leakage reduction coefficient is less than the first leakage reduction coefficient; and

repeating the steps of determining the current performance value, reducing the PMOS bias voltage, determining the first leakage reduction coefficient, and determining the second leakage reduction coefficient until either the current NMOS bias voltage is set to the maximum bias voltage of the plurality of bias voltages or the second leakage reduction coefficient is less than the first leakage reduction coefficient.

19. The method of claim 16, wherein receiving the plurality of leakage reduction coefficients further comprises:

measuring leakage currents of at least the biasable NMOS transistors; and

receiving leakage reduction coefficients corresponding to the measured leakage currents.

20. The method of claim 16, wherein receiving the plurality of leakage reduction coefficients further comprises:

performing simulations to obtain simulated leakage currents of at least the biasable NMOS transistors; and

receiving leakage reduction coefficients corresponding to the simulated leakage currents.

21. The method of claim 16, wherein receiving the plurality of leakage reduction coefficients further comprises:

measuring leakage currents of at least the biasable PMOS transistors; and

receiving leakage reduction coefficients corresponding to the measured leakage currents.

22. The method of claim 16, wherein receiving the plurality of leakage reduction coefficients further comprises:

performing simulations to obtain simulated leakage currents of at least the biasable PMOS transistors; and

receiving leakage reduction coefficients corresponding to the simulated leakage currents.

23. The method of claim 16, wherein receiving the plurality of leakage reduction coefficients further comprises:

receiving a plurality of leakage reduction tables, each leakage reduction table corresponding to a specified process skew factor;

measuring a die skew factor of the integrated circuit using a skew measurement circuit;

selecting a leakage reduction table of the plurality of leakage reduction tables based on the measured die skew factor; and

receiving the leakage reduction coefficients of the selected leakage reduction table.

24. The method of claim 23, wherein measuring the die skew factor further comprises measuring the die skew factor using a plurality of skewed ring oscillators.

25. The method of claim 23, wherein selecting the leakage reduction table further comprises interpolating between the plurality of leakage reduction tables based on the measured die skew factor.

26. The method of claim 23, wherein the leakage reduction coefficients reflect the number of PMOS transistors and the number of NMOS transistors on the IC.

27. The method of claim 23, wherein the leakage reduction coefficients reflect a leakage current of stacked NMOS or PMOS transistors.

28. The method of claim 16, wherein receiving the plurality of performance values further comprises:

coupling the plurality of body bias voltages to emulation circuits on an IC, the emulation circuits having structures corresponding to operational circuits on the IC; and

receiving a plurality of performance values obtained from evaluating performance of the emulation circuits under the plurality of body bias voltages coupled to the emulation circuits.

29. The method of claim 28, wherein:

coupling the plurality of body bias voltages to the emulation circuits comprises applying the plurality of body bias voltages to ring oscillator circuits that are included in the emulation circuits of the IC; and

evaluating performance of the emulation circuits comprises generating count values based on a frequency of the ring oscillator circuits.