Word line driver

• US 8,995,219 B2
• Filed: 03/28/2012
• Issued: 03/31/2015
• Est. Priority Date: 03/28/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Romanovskyy, Sergiy
• Primary Examiner(s): Hur, J. H.
• Application Number:
  US13/433,075
• Publication Number:
  US 20130258797A1
• Time in Patent Office: 1,098 Days
• Field of Search: 365/230.06, 365/185.23, 365/189.11, 365/149
• US Class Current: 365/230.06
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A first circuit is coupled to a second circuit, which is coupled to a third circuit. A high voltage value of a first input signal and of a first output signal of the first circuit are equal, and are less than a high voltage value of a second output signal of the second circuit. A low voltage value of the first input signal is higher than a low voltage value of the first output signal. A high voltage value of the second output signal and of a third output signal of the third circuit are equal. The low voltage value of the first output signal, the second output signal, and the third output signal are equal.

Claims

1. A word line driver circuit comprising:

a first circuit configured to receive a first input signal and to generate a first output signal, the first input signal swinging between a high voltage value and a low voltage value of the first input signal, the first output signal swinging between a high voltage value and a low voltage value of the first output signal;

a second circuit coupled to the first circuit and configured to receive the first output signal at an input of the second circuit and to generate a second output signal at an output of the second circuit, the second output signal swinging between a high voltage value and a low voltage value of the second output signal, and the input and the output of the second circuit being configured to be free from having a positive feedback path; and

a third circuit coupled to the second circuit and configured to receive the second output signal and generate a third output signal, the third output signal swinging between a high voltage value and a low voltage value of the third output signal,

wherein

the high voltage value of the first input signal and of the first output signal are equal, and are less than the high voltage value of the second output signal;

the low voltage value of the first input signal is higher than the low voltage value of the first output signal;

the high voltage values of the second output signal and of the third output signal are equal; and

the low voltage values of the first output signal, the second output signal, and the third output signal are equal.

2. The word line driver circuit of claim 1, wherein the word line driver circuit is configured to meet at least one of the following conditions:

the first circuit includes a first inverter;

the second circuit includes a second inverter;

or

the third circuit includes a third inverter.

3. The word line driver circuit of claim 2, wherein the word line driver circuit is configured to meet at least one of the following conditions:

a P-side of the first inverter is stronger than an N-side of the first inverter;

or

an N-side of the second inverter is stronger than a P-side of the second inverter.

4. The word line driver circuit of claim 2, wherein the word line driver circuit is configured to meet at least one of the following conditions:

P-side and N-side transistors of the first inverter include a transistor having an operational voltage higher than an operational voltage of core transistors;

P-side and N-side transistors of the second inverter include a transistor having an operational voltage higher than the operational voltage of the core transistors;

or

P-side and N-side transistors of the third inverter include a transistor having an operational voltage higher than the operational voltage of the core transistors.

5. The word line driver circuit of claim 1, wherein the word line driver circuit is configured to meet at least one of the following conditions:

the first circuit includes at least two PMOS transistors that are coupled in series and that have an operational voltage corresponding to an operational voltage of core transistors, and the first circuit further includes an NMOS transistor coupled to the least two PMOS transistors and having an operational voltage higher than the operational voltage of the core transistors;

the second circuit includes a PMOS transistor having an operational voltage higher than the operational voltage of the core transistors, and coupled in series with an NMOS transistor having an operational voltage higher than the operational voltage of the core transistors;

or

the third circuit includes a PMOS transistor having an operational voltage higher than the operational voltage of the core transistors, and coupled in series with an NMOS transistor having an operational voltage higher than the operational voltage of the core transistors.

6. The word line driver circuit of claim 1, wherein

a P-side current of a P-side of the first circuit and an N-side current of an N-side of the first circuit are selected to maximize an output level of the first circuit;

or

a P-side current of a P-side of the second circuit and an N-side current of an N-side of the second circuit are selected based on a threshold voltage of an N-side transistor in the third circuit.

7. A word line driver circuit comprising:

a first inverter having a first input and a first output, the first input being configured to receive a control signal, and the first inverter being free from receiving another control signal;

a second inverter having a second input and a second output, the second input coupled to the first output; and

a third inverter having a third input and a third output, the third input coupled to the second output,

wherein

the third output is configured to provide a signal for a word line of a memory cell;

the first inverter includes

a P-side configured to receive a first P-side voltage value and having a first P-side driving capability; and

an N-side configured to receive a first N-side voltage value and having a first N-side driving capability weaker than the first P-side driving capability;

the second inverter includes

a P-side configured to receive a second P-side voltage value and having a second P-side driving capability; and

an N-side configured to receive a second N-side voltage value and having a second N-side driving capability stronger than the second P-side driving capability; and

the third inverter includes

a P-side configured to receive a third P-side voltage value; and

an N-side configured to receive a third N-side voltage value.

8. The word line driver circuit of claim 7, wherein the word line driver circuit is configured such that:

the first output swings between the first P-side voltage value and the first N-side voltage value;

the second output swings between the second P-side voltage value and the second N-side voltage value;

the third output swings between the third P-side voltage value and the third N-side voltage value;

the first N-side voltage value, the second N-side voltage value, and the third N-side voltage value are equal;

the first P-side voltage value is less than the second P-side voltage value; and

the second P-side voltage value equals the third P-side voltage value.

9. The word line driver circuit of claim 7, wherein

the word line driver circuit is configured to receive the control signal having a first input high voltage value and a first input low voltage value;

the first input high voltage value equals the first P-side voltage value;

the first P-side voltage value is less than the second P-side voltage value;

the second P-side voltage value equals the third P-side voltage value;

the first input low voltage value is higher than the first N-side voltage value; and

the first N-side voltage value, the second N-side voltage value, and the third N-side voltage value are equal.

10. The word line driver circuit of claim 7, wherein

each of the P-side of the first inverter, the second inverter, and the third inverter includes a PMOS transistor having an operational voltage higher than an operational voltage of core transistors;

and

each of the N-side of the first inverter, the second inverter, and the third inverter includes an NMOS transistor having an operational voltage higher than the operational voltage of the core transistors.

11. The word line driver circuit of claim 7, wherein

the P-side of the first inverter includes a first thin oxide PMOS transistor coupled in series with a second PMOS transistor having an operational voltage being the same as an operational voltage of core transistors;

each of the P-side of the second inverter and the third inverter include a PMOS transistor having an operational voltage higher than the operational voltage of the core transistors; and

each of the N-side of the first inverter, the second inverter, and the third inverter includes an NMOS transistor having an operational voltage higher than the operational voltage of the core transistors.

12. The word line driver circuit of claim 7, wherein

a P-side current of the P-side of the first inverter and an N-side current of the N-side of the first inverter are selected to maximize an output level of the first circuit;

and

a P-side current of the P-side of the second inverter and an N-side current of the N-side of the second inverter are selected based on a threshold voltage of an N-side transistor in the third inverter.

13. A word line driver circuit comprising:

a first circuit;

a second circuit coupled to the first circuit; and

a third circuit coupled to the second circuit and having a PMOS transistor coupled in series with an NMOS transistor at an output node;

wherein

the first circuit is configured to convert a low logical value of a first input to a high logical value of a first output of the first circuit;

the second circuit is configured to convert the high logical value of the first output to a low logical value of a second output of the second circuit, and the second input and the second output are configured to be free from having a positive feedback path;

the low logical value of the second output equals a voltage value at a source of the NMOS transistor; and

the output node is configured to provide a signal for a word line of a memory cell.

14. The word line driver circuit of claim 13, wherein

the first circuit includes an inverter having a P-side current of a P-side of the first circuit stronger than an N-side current of an N-side of the first circuit;

and

the second circuit includes an inverter having an N current of an N-side of the second circuit stronger than a P-side current of a P-side of the second circuit.

15. The word line driver circuit of claim 14, wherein

the P-side current of the P-side of the first circuit and the N-side current of the N-side of the first circuit are selected to maximize an output level of the first circuit;

and

the P-side current of the P-side of the second circuit and the N-side current of the N-side of the second circuit are selected based on a threshold voltage of an N-side transistor in the third circuit.

16. The word line driver circuit of claim 13, wherein

the first circuit includes an inverter having a first first-circuit PMOS transistor coupled in series with a second first-circuit PMOS transistor, which is coupled in series with a first first-circuit NMOS transistor;

the first and the second first-circuit PMOS transistors have an operational voltage being the same as an operational voltage of core transistors; and

the first first-circuit NMOS transistor has an operational voltage higher than the operational voltage of the core transistors.

17. The word line driver circuit of claim 16, wherein

the word line of the memory cell is electrically coupled with the memory cell through a PMOS pass gate transistor having an operational voltage higher than the operational voltage of the core transistors.

18. The word line driver circuit of claim 13, wherein

the first circuit includes a first inverter having a first PMOS transistor coupled in series with a first NMOS transistor having an operational voltage higher than the operational voltage of the core transistors;

the second circuit includes a second inverter having a second PMOS transistor having an operational voltage higher than the operational voltage of the core transistors, and coupled in series with a second NMOS transistor having an operational voltage higher than the operational voltage of the core transistors; and

the third circuit includes a third inverter having a third PMOS transistor having an operational voltage higher than the operational voltage of the core transistors, and coupled in series with a third NMOS transistor having an operational voltage higher than the operational voltage of the core transistors.

19. The word line driver circuit of claim 13, wherein

the first circuit includes a first PMOS transistor coupled in series with a first NMOS transistor, the first PMOS transistor configured to receive a first P-side voltage value, the first NMOS transistor configured to receive a first N-side voltage value;

the second circuit includes a second PMOS transistor coupled in series with a second NMOS transistor, the second PMOS transistor configured to receive a second P-side voltage value, the second NMOS transistor configured to receive a second N-side voltage value;

the PMOS transistor of the third circuit is configured to receive a third P-side voltage value, the NMOS transistor of the third circuit is configured to receive a third N-side voltage value;

the first P-side voltage value is less than the second P-side voltage value;

the second P-side voltage value equal the third P-side voltage value; and

the first N-side voltage value, the second N-side voltage value, and the third N-side voltage value are equal.

20. The circuit of claim 19, wherein

the low logical value of the first input is higher than the first N-side voltage value;

and

the high logical value of the first input is lower than the second P-side voltage value.