Specialized processing block for implementing floating-point multiplier with subnormal operation support

• US 8,996,600 B1
• Filed: 08/03/2012
• Issued: 03/31/2015
• Est. Priority Date: 08/03/2012
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Langhammer, Martin
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US13/566,256
• Time in Patent Office: 970 Days
• Field of Search: None
• US Class Current: 708/503
• CPC Class Codes: G06F 7/485 Adding; Subtracting G06F7/4833, G06F7/4836 take precedence
• CPC Class Codes: G06F 7/4876 Multiplying
• CPC Class Codes: G06F 7/49915 Mantissa overflow or underflow in handling floating-point numbers

Abstract

The functions available in a specialized processing block of a programmable device include floating-point operations, including support within the specialized processing block for subnormal operations. This is accomplished, in part, by borrowing an adder in the specialized processing block and using the adder to operate on output of a multiplier or other operator to compete a subnormal operation. Although the adder becomes unavailable to serve as an adder, the need to complete the operation in slower, more valuable general purpose logic is avoided. The adder and the other operator need not necessarily be located together in a specialized processing block.

Claims

1. Circuitry for operating on floating-point numbers, each of said floating-point numbers having a mantissa and an exponent, said circuitry comprising:

at least one operator having an operator output including mantissa data and exponent data; and

an adder having said operator output as an input, and including operating units that determine a plurality of functions of said exponent data;

wherein;

when an operation performed by said operator is a subnormal operation, said adder operates on said operator output to complete said subnormal operation based on said plurality of functions of said exponent data.

2. The circuitry of claim 1 wherein said operator is a multiplier.

3. The circuitry of claim 1 wherein said operator and said adder are included in a specialized processing block of a programmable integrated circuit device.

4. The circuitry of claim 1 wherein:

said adder includes at least one left-shifter and at least one right-shifter; and

when an operation performed by said operator is a subnormal operation, different ones of said plurality of functions of said exponent data determine an amount of right-shifting by said right shifter and an amount of left-shifting by said left shifter.

5. The circuitry of claim 4 wherein said plurality of functions of said exponent data include a difference between two exponents, a difference between ‘

1’ and

an exponent, and a product of ‘

−

1’ and

an exponent.

6. The circuitry of claim 5 wherein said plurality of functions of said exponent data further include a difference between an exponent and ‘

1’ and

a comparison between an exponent and a count of leading zeroes.

7. The circuitry of claim 1 further comprising gating for replacing an implied leading ‘

1’

in one of said floating point numbers with a leading ‘

0’

when an operation performed by said operator is a subnormal operation.

8. A method of using circuitry of a programmable integrated circuit device to operate on floating-point numbers, each of said floating-point numbers having a mantissa and an exponent, and said circuitry having at least one operator that has an output including mantissa data and exponent data, and having an adder;

said method comprising;

configuring said adder to operate on said output of said operator, including configuring operating units in said adder to determine a plurality of functions of said exponent data;

wherein;

operation of said adder on said output of said operator is configured so that when an operation performed by said operator is a subnormal operation, operation of said adder on said output of said operator completes said subnormal operation based on said plurality of functions of said exponent data.

9. The method of claim 8 further comprising:

when performing a normalized operation of said operator on said floating-point numbers, configuring said operator to operate on said numbers, and configuring said adder to add results from said operator to another adder input.

10. The method of claim 8 wherein:

said adder includes at least one left-shifter and at least one right-shifter; and

said configuring operation of said adder on said output of said operator to complete said subnormal operation comprises;

configuring different ones of said plurality of functions of said exponent data to determine an amount of right-shifting by said right shifter and an amount of left-shifting by said left shifter.

11. The method of claim 10 wherein said plurality of functions of said exponent data include a difference between two exponents, a difference between ‘

1’ and

an exponent, and a product of ‘

−

1’ and

an exponent.

12. The method of claim 11 wherein said plurality of functions of said exponent data further include a difference between an exponent and ‘

1’ and

a comparison between an exponent and a count of leading zeroes.

13. The method of claim 8 further comprising configuring gating of said specialized processing block to replace an implied leading ‘

1’

in one of said floating point numbers with a leading ‘

0’

when an operation performed by said operator is a subnormal operation.

14. A non-transitory machine readable data storage medium encoded with instructions for performing a method of using circuitry of a programmable integrated circuit device to operate on floating-point numbers, each of said floating-point numbers having a mantissa and an exponent, and said circuitry having at least one operator that has an output including mantissa data and exponent data, and having an adder;

said instructions comprising;

instructions to configure said adder to operate on said output of said operator, including configuring operating units in said adder to determine a plurality of functions of said exponent data;

wherein;

operation of said adder on said output of said operator is configured by said instructions so that when an operation performed by said operator is a subnormal operation, operation of said adder on said output of said operator completes said subnormal operation based on said plurality of functions of said exponent data.

15. The non-transitory machine readable data storage medium of claim 14 wherein said instructions further comprise instructions to, when performing a normalized operation on said floating-point numbers, configure said operator to operate on said numbers, and to configure said adder to add results from said operator to another adder input.

16. The non-transitory machine readable data storage medium of claim 14 wherein:

said operator output includes mantissa data and exponent data;

said adder includes at least one left-shifter and at least one right-shifter; and

said instructions that configure operation of said adder on said output of said operator configure different ones of said plurality of functions of said exponent data to determine an amount of right-shifting by said right shifter and an amount of left-shifting by said left shifter.

17. The non-transitory machine readable data storage medium of claim 16 wherein said plurality of functions of said exponent data include a difference between two exponents, a difference between ‘

1’ and

an exponent, and a product of ‘

−

1’ and

an exponent.

18. The non-transitory machine readable data storage medium of claim 17 wherein said plurality of functions of said exponent data further include a difference between an exponent and ‘

1’ and

a comparison between an exponent and a count of leading zeroes.

19. The non-transitory machine readable data storage medium of claim 17 further comprising instructions to configure gating of said specialized processing block to replace an implied leading ‘

1’

in one of said floating point numbers with a leading ‘

0’

when an operation performed by said operator is a subnormal operation.