×

Integrated storage/processing devices, systems and methods for performing big data analytics

  • US 8,996,781 B2
  • Filed: 11/06/2012
  • Issued: 03/31/2015
  • Est. Priority Date: 11/06/2012
  • Status: Active Grant
First Claim
Patent Images

1. An integrated storage/processing system for use in a host computer system having a printed circuit board with a central processing unit, system memory, and an expansion bus mounted thereon, the integrated storage/processing system comprising:

  • at least a first expansion board adapted to be connected to the expansion bus of the host computer system, the first expansion board having mounted thereon a graphics processing unit configured for general purpose computing and a local frame buffer comprising volatile memory devices;

    a non-volatile memory array functionally coupled to the graphics processing unit and configured to allow direct data transfers from the non-volatile memory array to the graphics processing unit without routing the transferred data through the system memory of the printed circuit board, the non-volatile memory array being configured to receive sets of big data from the host computer system via the expansion bus thereof; and

    a non-volatile memory controller that accesses the non-volatile memory array;

    wherein the expansion bus of the host computer system comprises a PCIe bus connector functionally coupled to a PCIe root complex on the printed circuit board and the first expansion board interfaces with the host computer system through the PCIe bus connector, and wherein the integrated storage/processing system meets one of the follow requirements;

    (a) the PCIe bus connector is a single-slot PCIe bus connector divided into first and second groups of PCIe lanes, the first group of PCIe lanes is coupled to the graphics processing unit, and the second group of PCIe lanes is coupled to the non-volatile memory controller, the integrated storage/processing system further comprising a third group of PCIe lanes that directly couples the graphics processing unit to the non-volatile memory controller;

    or(b) the integrated storage/processing system further comprises a PCIe switch coupled to the non-volatile memory controller, the PCIe bus connector is a single-slot PCIe bus connector divided into first and second groups of PCIe lanes, the first group of PCIe lanes is coupled to the graphics processing unit, the second group of PCIe lanes is coupled to the PCIe switch, the PCIe switch is coupled to the non-volatile memory controller through a third group of PCIe lanes and to the graphics processing unit through a fourth group of PCIe lanes, and the PCIe switch routes transfer of data between the graphics processing unit, the non-volatile memory controller, and the PCIe bus connector;

    or(c) the non-volatile memory array uses NVM Express standard to interface with the non-volatile memory controller;

    or(d) the non-volatile memory controller implements SCSI express standard for SCSI commands over PCIe lanes.

View all claims
  • 13 Assignments
Timeline View
Assignment View
    ×
    ×