Integrated storage/processing devices, systems and methods for performing big data analytics
First Claim
Patent Images
1. An integrated storage/processing system for use in a host computer system having a printed circuit board with a central processing unit, system memory, and an expansion bus mounted thereon, the integrated storage/processing system comprising:
- at least a first expansion board adapted to be connected to the expansion bus of the host computer system, the first expansion board having mounted thereon a graphics processing unit configured for general purpose computing and a local frame buffer comprising volatile memory devices;
a non-volatile memory array functionally coupled to the graphics processing unit and configured to allow direct data transfers from the non-volatile memory array to the graphics processing unit without routing the transferred data through the system memory of the printed circuit board, the non-volatile memory array being configured to receive sets of big data from the host computer system via the expansion bus thereof; and
a non-volatile memory controller that accesses the non-volatile memory array;
wherein the expansion bus of the host computer system comprises a PCIe bus connector functionally coupled to a PCIe root complex on the printed circuit board and the first expansion board interfaces with the host computer system through the PCIe bus connector, and wherein the integrated storage/processing system meets one of the follow requirements;
(a) the PCIe bus connector is a single-slot PCIe bus connector divided into first and second groups of PCIe lanes, the first group of PCIe lanes is coupled to the graphics processing unit, and the second group of PCIe lanes is coupled to the non-volatile memory controller, the integrated storage/processing system further comprising a third group of PCIe lanes that directly couples the graphics processing unit to the non-volatile memory controller;
or(b) the integrated storage/processing system further comprises a PCIe switch coupled to the non-volatile memory controller, the PCIe bus connector is a single-slot PCIe bus connector divided into first and second groups of PCIe lanes, the first group of PCIe lanes is coupled to the graphics processing unit, the second group of PCIe lanes is coupled to the PCIe switch, the PCIe switch is coupled to the non-volatile memory controller through a third group of PCIe lanes and to the graphics processing unit through a fourth group of PCIe lanes, and the PCIe switch routes transfer of data between the graphics processing unit, the non-volatile memory controller, and the PCIe bus connector;
or(c) the non-volatile memory array uses NVM Express standard to interface with the non-volatile memory controller;
or(d) the non-volatile memory controller implements SCSI express standard for SCSI commands over PCIe lanes.
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Accused Products
Abstract
Architectures and methods for performing big data analytics by providing an integrated storage/processing system containing non-volatile memory devices that form a large, non-volatile memory array and a graphics processing unit (GPU) configured for general purpose (GPGPU) computing. The non-volatile memory array is directly functionally coupled (local) with the GPU and optionally mounted on the same board (on-board) as the GPU.
29 Citations
49 Claims
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1. An integrated storage/processing system for use in a host computer system having a printed circuit board with a central processing unit, system memory, and an expansion bus mounted thereon, the integrated storage/processing system comprising:
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at least a first expansion board adapted to be connected to the expansion bus of the host computer system, the first expansion board having mounted thereon a graphics processing unit configured for general purpose computing and a local frame buffer comprising volatile memory devices; a non-volatile memory array functionally coupled to the graphics processing unit and configured to allow direct data transfers from the non-volatile memory array to the graphics processing unit without routing the transferred data through the system memory of the printed circuit board, the non-volatile memory array being configured to receive sets of big data from the host computer system via the expansion bus thereof; and a non-volatile memory controller that accesses the non-volatile memory array; wherein the expansion bus of the host computer system comprises a PCIe bus connector functionally coupled to a PCIe root complex on the printed circuit board and the first expansion board interfaces with the host computer system through the PCIe bus connector, and wherein the integrated storage/processing system meets one of the follow requirements; (a) the PCIe bus connector is a single-slot PCIe bus connector divided into first and second groups of PCIe lanes, the first group of PCIe lanes is coupled to the graphics processing unit, and the second group of PCIe lanes is coupled to the non-volatile memory controller, the integrated storage/processing system further comprising a third group of PCIe lanes that directly couples the graphics processing unit to the non-volatile memory controller;
or(b) the integrated storage/processing system further comprises a PCIe switch coupled to the non-volatile memory controller, the PCIe bus connector is a single-slot PCIe bus connector divided into first and second groups of PCIe lanes, the first group of PCIe lanes is coupled to the graphics processing unit, the second group of PCIe lanes is coupled to the PCIe switch, the PCIe switch is coupled to the non-volatile memory controller through a third group of PCIe lanes and to the graphics processing unit through a fourth group of PCIe lanes, and the PCIe switch routes transfer of data between the graphics processing unit, the non-volatile memory controller, and the PCIe bus connector;
or(c) the non-volatile memory array uses NVM Express standard to interface with the non-volatile memory controller;
or(d) the non-volatile memory controller implements SCSI express standard for SCSI commands over PCIe lanes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. An integrated storage/processing system for use in a host computer system having a printed circuit board with a central processing unit, system memory, and a PCIe expansion bus mounted thereon, the integrated storage/processing system comprising a processor expansion board that comprises:
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a PCIe-based edge connector adapted to communicate signals with the host computer system through the PCIe expansion bus of the host computer system; a local array of volatile memory devices; a non-volatile solid-state memory-based storage subsystem; non-volatile memory controller functionally coupled to the non-volatile solid-state memory-based storage subsystem; a hybrid processing unit having a general purpose computing core, a graphics processing core, an integrated memory controller coupled to the local array of volatile memory devices, and an integrated PCIe root complex coupled to the non-volatile solid-state memory-based storage subsystem; and a non-transparent bridge that couples the hybrid processing unit to the PCIe-based edge connector. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A method for analyzing big data using an integrated storage/processing system in a host computer system having a printed circuit board with a central processing unit, system memory, and an expansion bus mounted thereon, the method comprising:
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transmitting sets of big data from the host computer system via the expansion bus thereof to a non-volatile memory array of the integrated storage/processing system, the integrated storage/processing system comprising a printed circuit board having mounted thereon a graphics processing unit configured for general purpose computing, a local frame buffer comprising volatile memory devices, and the non-volatile memory array functionally coupled to the graphics processing unit; performing direct data transfers from the non-volatile memory array to the graphics processing unit without routing the transferred data through the system memory of the host computer system; and accessing the non-volatile memory array with a non-volatile memory controller; wherein the expansion bus of the host computer system comprises a PCIe bus connector functionally coupled to a PCIe root complex on the printed circuit board and the method further comprises interfacing the integrated storage/processing system with the host computer system through the PCIe bus connector, and wherein the method meets one of the follow requirements; (a) the PCIe bus connector is a single-slot PCIe bus connector divided into first and second groups of PCIe lanes, the first group of PCIe lanes being coupled to the graphics processing unit, the second group of PCIe lanes being coupled to the non-volatile memory controller, and a third group of PCIe lanes directly coupling the graphics processing unit to the non-volatile memory controller, or (b) the PCIe bus connector is a single-slot PCIe bus connector divided into first and second groups of PCIe lanes, the first group of PCIe lanes being coupled to the graphics processing unit, the second group of PCIe lanes being coupled to a PCIe switch, the PCIe switch being coupled to the non-volatile memory controller through a third group of PCIe lanes and to the graphics processing unit through a fourth group of PCIe lanes, the method further comprising using the PCIe switch to arbitrate transfers of data between the graphics processing unit, the non-volatile memory controller, and the PCIe bus connector, or (c) the method further comprises using NVM Express standard to interface the non-volatile memory array with the non-volatile memory controller, or (d) the method further comprises implementing SCSI express standard for SCSI commands over PCIe lanes with the non-volatile memory controller. - View Dependent Claims (30, 31, 32)
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33. A method for analyzing big data using an integrated storage/processing system in a host computer system having a printed circuit board with a central processing unit, system memory, and a PCIe bus connector mounted thereon, the method comprising:
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transmitting sets of big data from the host computer system via the PCIe bus connector thereof to a non-volatile memory array of the integrated storage/processing system, the integrated storage/processing system comprising; a graphics expansion card having mounted thereon a graphics processing unit configured for general purpose computing, a local frame buffer comprising volatile memory devices, and a PCIe-based edge connector coupled to the graphics processing unit; a solid-state drive comprising a second circuit board having mounted thereon the non-volatile memory array, a non-volatile memory controller functionally coupled to the non-volatile memory array, and a PCIe-based edge connector; and a daughter board comprising a PCIe switch, at least one PCIe-based edge connector coupled to the PCIe switch, and at least two PCIe-based expansion slots coupled to the PCIe switch and arbitrating signals between the PCIe-based edge connector of the daughter board and the PCIe-based expansion slots of the daughter board, the PCIe-based edge connector of the graphics expansion card being received in at least one of the PCIe-based expansion slots of the daughter board and the PCIe-based edge connector of the second expansion card being received in at least one of the PCIe-based expansion slots of the daughter board; and performing direct data transfers from the non-volatile memory array to the graphics processing unit through the PCIe switch without routing the transferred data through the system memory of the host computer system. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40)
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41. A method for analyzing big data using an integrated storage/processing system in a host computer system having a printed circuit board with a central processing unit, system memory, and a PCIe expansion bus mounted thereon, the integrated storage/processing system comprising:
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a graphics expansion card having mounted thereon a graphics processing unit configured for general purpose computing, a local frame buffer comprising volatile memory devices, a PCIe-based edge connector coupled to the graphics processing unit and coupled to a first PCIe expansion slot of the PCIe expansion bus of the host computer system, and a second connector adapted to transfer PCIe signals; a solid-state drive comprising a second expansion card having mounted thereon the non-volatile memory array, a non-volatile memory controller functionally coupled to the non-volatile memory array, a PCIe-based edge connector coupled to the graphics processing unit through a second PCIe expansion slot of the PCIe expansion bus of the host computer system, and a second connector adapted to transfer PCIe signals; and a bridge board comprising a transparent PCIe switch and at least two connectors that are coupled to the PCIe switch and mate with the second connectors of the graphics expansion card and the solid-state drive; the method comprising; transmitting sets of big data from the host computer system via the PCIe expansion bus thereof to the non-volatile memory array of the solid-state drive; and exchanging signals between the graphics expansion card and the solid state drive with the bridge board without accessing the first and second PCIe expansion slots of the host computer system.
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42. A method for analyzing big data using an integrated storage/processing system in a host computer system having a printed circuit board with a central processing unit, system memory, and a PCIe expansion bus mounted thereon, the integrated storage/processing system comprising a processor expansion board that comprises:
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a PCIe-based edge connector adapted to communicate signals with the host computer system through the PCIe expansion bus of the host computer system; a local array of volatile memory devices; a non-volatile solid-state memory-based storage subsystem; non-volatile memory controller functionally coupled to the non-volatile solid-state memory-based storage subsystem; a hybrid processing unit having a general purpose computing core, a graphics processing core, an integrated memory controller coupled to the local array of volatile memory devices, and an integrated PCIe root complex coupled to the non-volatile solid-state memory-based storage subsystem; and a non-transparent bridge that couples the hybrid processing unit to the PCIe-based edge connector; the method comprising; transmitting sets of big data from the host computer system via the PCIe expansion bus thereof to the non-volatile memory array of the integrated storage/processing system; and performing direct data transfers from the non-volatile memory array to the graphics processing unit without routing the transferred data through the system memory of the host computer system. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49)
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Specification