Memory access system

• US 8,996,817 B2
• Filed: 07/12/2012
• Issued: 03/31/2015
• Est. Priority Date: 07/12/2012
• Status: Active Grant

• Current Assignee: Harman International Industries Incorporated (Samsung Electronics Co. Ltd.)
• Original Assignee: Harman International Industries Incorporated (Samsung Electronics Co. Ltd.)
• Inventors: Bushen, Kirk I.
• Primary Examiner(s): Parikh, Kalpit
• Application Number:
  US13/547,278
• Publication Number:
  US 20140019703A1
• Time in Patent Office: 992 Days
• Field of Search: 711/167, 711/138, 710/18
• US Class Current: 711/138
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1673 using buffers

Abstract

A memory access system may be used to relay data between an electronic device and external memory. The memory access system may include write buffers which may receive and write information from the electronic device to the external memory. The memory access system may also include read buffers which may gather data from the external memory and send it to a main processing component of the electronic device for processing. The memory access system may be configured so that the main processing component of the electronic device may gather data from the write buffers of the memory access system when a condition is satisfied.

Claims

1. A memory access system, comprising:

a write buffer component in communication with a processor and a memory separate from the processor, the write buffer component configured to receive first data from the processor and transmit the first data to the memory; and

a read buffer component in communication with the processor and the memory, the read buffer component configured to gather second data from the memory to transmit the second data to the processor;

where the write buffer is configured to bypass the memory and to transmit the first data to the processor when a condition specifying a maximum amount of delay index before the memory is utilized is satisfied by a delay index of the first data.

2. The memory access system of claim 1, where the condition is satisfied when the delay index of the first data is less than a threshold value minus one.

3. The memory access system of claim 2, where the threshold value corresponds to twice a predetermined size of the first data.

4. The memory access system of claim 1, where the first data comprises:

a first set of samples processed by the processor during a first clock cycle;

a second set of samples processed by the processor during a second clock cycle after the first clock cycle; and

a third set of samples processed by the processor during a third clock cycle after the second clock cycle.

5. The memory access system of claim 4, where the write buffer component comprises a first buffer, a second buffer, and a third buffer;

and

where the write buffer component is configured to write the first set of samples to the first buffer, the second set of samples to the second buffer, and the third set of samples to the third buffer.

6. The memory access system of claim 5, where the first data comprises a fourth set of samples processed by the processor during a fourth clock cycle after the third clock cycle, and where the write buffer component is configured to write the fourth set of samples to the first buffer.

7. A method of accessing data, comprising:

storing data from a first processing component in a write buffer component;

writing the data from the write buffer component to a memory separate from the first processing component;

gathering the data from the memory with a read buffer component;

accessing the data for use with a second processing component using the write buffer component when a first condition specifying a maximum amount of delay index before the memory is utilized is satisfied by a delay index for the data, the second processing component being separate from the first processing component and the memory; and

accessing the data for use with the second processing component using the read buffer component when the condition is not satisfied.

8. The method of claim 7, further comprising:

satisfying the condition when delay index for the data is not greater than a threshold value.

9. The method of claim 8, where the data comprises a set of samples, and where the threshold value is equal to twice a size of the set of samples minus one.

10. The method of claim 7, further comprising storing the data from the first processing component in the write buffer component at least one clock cycle before the data is written from the write buffer component to memory separate from the first processing component.

11. The method of claim 7, further comprising determining, during each clock cycle, when the condition is satisfied.

12. The method of claim 11, where the data for use with the second processing component is accessed during each clock cycle according to the determination.

13. An electronic device, comprising:

a processing component;

a memory separate from the processing component; and

a memory access component in communication with the processing component and the memory, the memory access component including;

a write buffer component configured to receive first data from the processing component and to transmit the first data to the memory; and

a read buffer component configured to gather second data from the memory to transmit the second data to the processing component; and

where the processing component is configured to receive the first data from the write buffer when a condition specifying a maximum amount of delay index before the memory is utilized is satisfied by a delay index for the first data, and where the processing component is configured to receive the second data from the read buffer when the condition is not satisfied.

14. The electronic device of claim 13, where the write buffer component is configured to receive the first data and the read buffer component gathers the second data during each clock cycle.

15. The electronic device of claim 14, further comprising a memory access control component configured to determine when the condition is satisfied.

16. The electronic device of claim 15, where the memory access control component determines when the condition is satisfied during each clock cycle.

17. The electronic device of claim 14, where the write buffer component comprises a first write buffer configured to receive the first data during a first clock cycle, a second write buffer configured to receive the first data during a second clock cycle after the first clock cycle, and a third write buffer configured to receive the first data during a third clock cycle after the second clock cycle.

18. The electronic device of claim 17, where the first write buffer is configured to receive fourth data during a fourth clock cycle after the third clock cycle.

19. The electronic device of claim 13, where the first data and the second data are a substantially the same size, and where the condition is satisfied when a delay index for the first data is less than twice the size minus one.

20. The electronic device of claim 13, where the write buffer component is configured to receive the first data from a sample processing component of the processing component;

and

where a main processing component of the processing component receives the first data from the write buffer in response to satisfaction of the condition, and receives the second data from the read buffer when the condition is not satisfied.