Structure variation detection for a memory having a three-dimensional memory configuration

• US 8,996,838 B1
• Filed: 05/08/2014
• Issued: 03/31/2015
• Est. Priority Date: 05/08/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: D'Abreu, Manuel Antonio, Hu, Xinde
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US14/273,031
• Time in Patent Office: 327 Days
• Field of Search: 711/103, 711/154, 711/170, 365/185.12, 365/189.09, 714/773
• US Class Current: 711/170
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 2029/0407 on power on
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A data storage device includes a memory having a three-dimensional (3D) memory configuration. The memory includes a structure that extends through multiple layers of the memory. A method includes storing information at the data storage device. The information identifies a location associated with a variation of the structure. The method further includes accessing the information.

Claims

1. A method comprising:

in a data storage device that includes a memory having a three-dimensional (3D) memory configuration and including a structure extending through multiple layers of the memory, performing;

storing information at the data storage device, the information identifying a location associated with a variation of the structure; and

accessing the information.

2. The method of claim 1, wherein the structure includes a conductive channel and a charge trap structure, and wherein the variation corresponds to a difference between a first width of the structure at a first distance from a substrate of the memory and a second width of the structure at a second distance from the substrate, the second distance greater than the first distance.

3. The method of claim 1, further comprising:

measuring a first parameter of a first storage element associated with a first layer of the memory;

measuring a second parameter of a second storage element associated with a second layer of the memory; and

determining whether a difference between the first parameter and the second parameter satisfies a threshold.

4. The method of claim 3, wherein the first parameter corresponds to a first number of programming pulses applied to the first storage element to program the first storage element to a particular threshold voltage, and wherein the second parameter corresponds to a second number of programming pulses applied to the second storage element to program the second storage element to the particular threshold voltage.

5. The method of claim 3, further comprising determining that the location is above the first layer and the second layer in response to determining that the difference fails to satisfy the threshold.

6. The method of claim 3, wherein the difference satisfies the threshold, and further comprising determining that the location is between the first layer and the second layer in response to determining that the difference satisfies the threshold.

7. The method of claim 6, further comprising:

in response to determining the location, generating the information; and

storing the information at the data storage device.

8. The method of claim 7, wherein the data storage device further includes a controller that is operationally coupled to the memory, wherein the information is stored at the memory, and wherein the controller accesses the information from the memory.

9. The method of claim 1, wherein the information is generated in response to an initial power-up of the data storage device.

10. The method of claim 1, further comprising adjusting a power-up indicator stored at the data storage device from a first value to a second value after determining the location.

11. The method of claim 1, wherein the memory is a non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate, and wherein the data storage device further includes circuitry associated with operation of the memory cells.

12. A data storage device comprising:

a memory having a three-dimensional (3D) memory configuration and including a structure extending through multiple layers of the memory; and

a controller coupled to the memory, wherein the controller is configured to access information that is stored at the memory, the information identifying a location associated with a variation of the structure.

13. The data storage device of claim 12, wherein the structure includes a conductive channel and a charge trap structure, and wherein the variation is a difference between a first width of the structure at a first distance from a substrate of the memory and a second width of the structure at a second distance from the substrate, the second distance greater than the first distance.

14. The data storage device of claim 12, wherein the controller is further configured to measure a first parameter of a first storage element associated with a first layer of the memory, to measure a second parameter of a second storage element associated with a second layer of the memory, and to determine whether a difference between the first parameter and the second parameter satisfies a threshold.

15. The data storage device of claim 14, wherein the first parameter corresponds to a first number of programming pulses applied to the first storage element to program the first storage element to a particular threshold voltage, and wherein the second parameter corresponds to a second number of programming pulses applied to the second storage element to program the second storage element to the particular threshold voltage.

16. The data storage device of claim 14, wherein the difference fails to satisfy the threshold, and wherein the controller is further configured to determine that the location is above the first layer and the second layer in response to determining that the difference fails to satisfy the threshold.

17. The data storage device of claim 14, wherein the difference satisfies the threshold, and wherein the controller is further configured to determine that the location is between the first layer and the second layer in response to determining that the difference satisfies the threshold.

18. The data storage device of claim 17, wherein the controller is further configured to generate the information in response to an initial power-up of the data storage device.

19. The data storage device of claim 12, wherein the controller is further configured to generate the information in response to determining the location and to store the information at the memory.

20. The data storage device of claim 12, wherein the memory is a non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate, and further comprising circuitry associated with operation of the memory cells.