Systems and methods for initializing regions of a flash drive having diverse error correction coding (ECC) schemes

• US 8,996,957 B1
• Filed: 05/22/2012
• Issued: 03/31/2015
• Est. Priority Date: 05/22/2012
• Status: Active Grant

• Current Assignee: Ip Gem Group, LLC
• Original Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Inventors: Northcott, Philip L.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): DORMAN, CHRISTIAN M
• Application Number:
  US13/477,633
• Time in Patent Office: 1,043 Days
• Field of Search: 714/752, 714/763, 714/773, 714/774
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2927 Decoding strategies
• CPC Class Codes: H03M 13/2945 using at least three error correction codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2963 Turbo-block codes, i.e. turbo codes based on block codes, e.g. turbo decoding of product codes
• CPC Class Codes: H03M 13/35 Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics

Abstract

Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.

Claims

1. A method of selecting among gears, wherein different gears correspond to different error correction coding (ECC) schemes for regions of a flash drive, the method comprising:

performing a memory test to determine raw bit error rates among the regions of the flash drive, wherein performing the memory test further comprises;

encoding data only with a gear having the highest amount of correction ability for all the regions regardless of the current gear setting(s) for the regions;

programming the encoded data;

retrieving the encoded data;

performing error correction such that errors encountered can be counted;

determining a raw bit error rate (RBER) based on the counted errors;

retiring regions having an RBER above a selected threshold; and

for remaining regions, allocating one or more regions to one of at least a first gear or a second gear based at least partly on the RBER for the region, wherein the first gear and the second gear vary by data payload size and correction capability; and

initiating the method at least partly in response to receiving an instruction to perform formatting;

wherein the memory test, retiring regions, and allocating are performed by an integrated circuit.

2. The method of claim 1, wherein performing the memory test further comprises applying a test pattern to the regions, counting errors encountered, and determining the RBER based on the counted errors.

3. The method of claim 1, wherein performing the memory test further comprises:

scrambling data corresponding to all zeroes;

encoding the scrambled data with the gear having the highest amount of correction ability; and

determining the RBER based on the counted errors.

4. The method of claim 3, wherein the errors are counted by counting ones in the corrected data.

15. The method of claim 1, wherein the memory test, retiring regions, and allocating are performed concurrently with initialization operations for an end user.

5. An apparatus comprising:

a first circuit configured to initiate a memory test at least partly in response to an instruction to perform formatting to determine raw bit error rates among regions of a flash drive, wherein to run the memory test, the first circuit is configured to;

encode data only with a gear having the highest amount of correction ability for all the regions regardless of the current gear setting(s) for the regions;

program the encoded data;

retrieve the encoded data;

perform error correction such that errors encountered can be counted; and

determine a raw bit error rate (RBER) based on the counted errors; and

a second circuit configured to;

retire regions having a RBER above a selected threshold; and

allocate one or more remaining regions to one of at least a first gear or a second gear based at least partly on the RBER for the region, wherein the first gear and the second gear vary by data payload size and correction capability, wherein different gears correspond to different error correction coding (ECC) schemes for regions of the flash drive.

6. The apparatus of claim 5, wherein the first circuit is further configured to apply a test pattern to the regions, to count errors encountered, and to determine the RBER based on the counted errors.

7. The apparatus of claim 5, wherein the first circuit is further configured to:

scramble data corresponding to all zeroes;

encode the scrambled data with the gear having the highest amount of correction ability; and

determine the RBER based on the counted errors.

8. The apparatus of claim 7, wherein the first circuit is configured to count ones in the corrected data to count errors.

9. The apparatus of claim 5, further comprising a plurality of flash memory devices, wherein the apparatus comprises the flash drive.

16. The apparatus of claim 5, wherein the first circuit is configured to run the memory test concurrently with initialization operations for an end user.

10. An apparatus for selecting among gears, wherein different gears correspond to different error correction coding (ECC) schemes for regions of a flash drive, the apparatus comprising:

a means for performing a memory test configured to determine raw bit error rates among the regions of the flash drive, wherein the memory test performing means is configured to;

initiate the memory test at least partly in response to receiving an instruction to perform formatting;

encode data only with a gear having the highest amount of correction ability for all the regions regardless of the current gear setting(s) for the regions;

program the encoded data;

retrieve the encoded data;

perform error correction such that errors encountered can be counted; and

determine a raw bit error rate (RBER) based on the counted errors;

a means for retiring regions having an RBER above a selected threshold; and

a means for allocating one or more remaining regions to one of at least a first gear or a second gear based at least partly on the RBER for the region, wherein the first gear and the second gear vary by data payload size and correction capability.

11. The apparatus of claim 10, wherein the memory test performing means is configured to apply a test pattern to the regions, count errors encountered, and determine the RBER based on the counted errors.

12. The apparatus of claim 10, wherein the memory test performing means is further configured to:

scramble data corresponding to all zeroes;

encode the scrambled data with the gear having the highest amount of correction ability; and

determine the RBER based on the counted errors.

13. The apparatus of claim 12, wherein memory test performing means is further configured to count the errors by counting ones in the corrected data.

14. The apparatus of claim 10, further comprising a plurality of flash memory devices, wherein the apparatus comprises the flash drive.

17. The apparatus of claim 10, wherein the memory test performing means is further configured to run the memory test concurrently with initialization operations for an end user.