Techniques for generating a single configuration file for multiple partial reconfiguration regions

• US 8,997,033 B1
• Filed: 03/05/2014
• Issued: 03/31/2015
• Est. Priority Date: 03/05/2014
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Hew, Yin Chong
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US14/197,918
• Time in Patent Office: 391 Days
• Field of Search: 326/37, 326/38, 326/41, 716116-117, 716/138, 717/136, 717/140
• US Class Current: 716/116
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing

Abstract

Techniques for compiling an integrated circuit (IC) design with a computer-aided design tool are provided. The IC design may include multiple dynamic configuration regions that may be updated during runtime without affecting other regions on the IC device. When an IC design is compiled for an IC device, dynamic configuration regions in the IC design are identified. The computer-aided design tool may generate a partial configuration file for each identified dynamic configuration region. Two or more partial reconfiguration files may be combined to obtain a single partial configuration file that may then be used to configure respective dynamic configuration regions on the IC device.

Claims

1. A method of compiling an integrated circuit design, comprising:

with a computer-aided design tool implemented on computing equipment, identifying a plurality of dynamic configuration regions in the integrated circuit design;

for each identified dynamic configuration region of the plurality of dynamic configuration regions in the integrated circuit design, generating a partial configuration file;

combining at least two partial configuration files to obtain a single partial configuration file for at least two respective dynamic configuration regions in the plurality of dynamic configuration regions;

for each identified dynamic configuration region of the plurality of dynamic configuration regions, generating a settings file prior to generating the partial configuration file; and

generating a full-chip binary configuration file based on the integrated circuit design prior to combining the at least two partial configuration files, wherein generating the partial configuration file comprises combining at least a portion of the full-chip binary configuration file and the settings file to obtain the partial configuration file for each identified dynamic configuration region.

2. The method defined in claim 1, wherein the partial configuration file comprises a plurality of binary bits, and wherein combining the at least two partial configuration files comprises:

performing an OR operation on respective binary bits in the at least two partial configuration files, wherein the single partial configuration file contains results of the OR operation on the respective binary bits.

3. The method defined in claim 1 further comprising:

receiving user input; and

selecting the at least two partial configuration files that are combined into the single partial configuration file based at least partly on the received user input.

4. The method defined in claim 1 further comprising:

identifying an error in one of the at least two configuration files prior to combining the at least two partial configuration files; and

in response to identifying the error, outputting an error message.

5. The method defined in claim 4, wherein each of the at least two configuration files comprises an array of binary bits, and wherein identifying the error comprises:

identifying overlapping logic high bits in the array of binary bits in the at least two configuration files.

6. A method of generating a single configuration file associated with at least two dynamic configuration regions on an integrated circuit device, the method comprising:

with a computer-aided design tool implemented on a computer, receiving an integrated circuit design for the integrated circuit device;

identifying the at least two dynamic configuration regions in the integrated circuit design;

generating respective settings files for the at least two dynamic configuration regions, wherein each of the respective settings files comprises a plurality of binary bits;

performing a legality check on the settings files to determine whether the respective settings files can be combined;

in response to passing the legality check, combining the respective settings files to generate a merged settings file by performing an OR operation on the plurality of binary bits in the respective settings files; and

generating the single configuration file based at least in part on the merged settings file, wherein the single configuration file is adapted to configure the at least two dynamic configuration regions on the integrated circuit device concurrently during runtime.

7. The method defined in claim 6 further comprising:

with the computer-aided design tool, compiling the received integrated circuit design to generate a full-chip binary configuration file for the integrated circuit device.

8. The method defined in claim 7, wherein generating the single configuration file comprises combining the merged settings file with at least a portion of the full-chip binary configuration file.

9. The method defined in claim 6 wherein performing the legality check on the settings files comprises:

identifying an error in the respective settings files prior to combining the respective settings files; and

in response to identifying the error, outputting an error message.

10. The method defined in claim 9, wherein each of the respective settings files comprises an array of binary bits, and wherein identifying the error comprises:

identifying overlapping logic high bits in the array of binary bits in the respective settings files.

11. Non-transitory computer-readable storage media for configuring an integrated circuit device, comprising instructions for:

receiving circuitry design data associated with an integrated circuit device having a plurality of partial reconfiguration regions;

generating partial reconfiguration bitstream files for respective partial reconfiguration regions of the plurality of partial reconfiguration regions;

combining at least two partial reconfiguration bitstream files for two respective partial reconfiguration regions to generate a merged partial reconfiguration bitstream file for the two respective partial reconfiguration regions;

after generating the partial reconfiguration bitstream files for the respective partial reconfiguration regions of the plurality of partial reconfiguration regions, receiving user input for selecting which of the partial reconfiguration bitstream files are to be combined; and

in response to receiving the user input, selecting the at least two partial reconfiguration bitstream files to be combined to generate the merged partial reconfiguration bitstream file.

12. The non-transitory computer-readable storage media defined in claim 11 further comprising instructions for:

generating settings files for the respective partial reconfiguration regions prior to generating the partial reconfiguration bitstream files.

13. The non-transitory computer-readable storage media defined in claim 12 further comprising instructions for:

compiling the received circuitry design data for the integrated circuit device;

generating a configuration bitstream file for the integrated circuit device based on the received circuitry design data; and

combining the configuration bitstream file with the settings files for the respective partial reconfiguration regions to generate the partial reconfiguration bitstream files.

14. The non-transitory computer-readable storage media defined in claim 11 further comprising instructions for:

comparing the at least two partial reconfiguration bitstream files with a set of predefined rules prior to combining the at least two partial reconfiguration bitstream files.

15. The non-transitory computer-readable storage media defined in claim 11, wherein the at least two partial reconfiguration bitstream files comprise a plurality of binary bits each, and wherein the instructions for combining the at least two partial reconfiguration bitstream files comprises instructions for performing an OR operation on respective binary bits in the at least two partial reconfiguration bitstream files.