Method for making oxide semiconductor device

• US 8,999,751 B2
• Filed: 02/18/2014
• Issued: 04/07/2015
• Est. Priority Date: 10/09/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Takahashi, Kei, Ito, Yoshiaki
• Primary Examiner(s): Hu, Shouxiang
• Application Number:
  US14/182,726
• Publication Number:
  US 20140162402A1
• Time in Patent Office: 413 Days
• Field of Search: 438/104, 438/150, 438/151, 438/157, 438/158, 438/479, 438/482, 438/483, 257/E21.09, 257/E21.59, 257/E29.068, 257/43, 257/72, 257/64, 257/66
• US Class Current: 438/104
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

It is an object to provide a semiconductor device having a new productive semiconductor material and a new structure. The semiconductor device includes a first conductive layer over a substrate, a first insulating layer which covers the first conductive layer, an oxide semiconductor layer over the first insulating layer that overlaps with part of the first conductive layer and has a crystal region in a surface part, second and third conductive layers formed in contact with the oxide semiconductor layer, an insulating layer which covers the oxide semiconductor layer and the second and third conductive layers, and a fourth conductive layer over the insulating layer that overlaps with part of the oxide semiconductor layer.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first conductive layer over a substrate;

forming a first insulating layer over the first conductive layer;

forming an oxide semiconductor layer over the first insulating layer, the oxide semiconductor layer overlapping the first conductive layer;

heating the oxide semiconductor layer to increase crystallinity of the oxide semiconductor layer;

forming a second conductive layer and a third conductive layer which are in contact with the oxide semiconductor layer;

forming a second insulating layer over the oxide semiconductor layer, the second conductive layer, and the third conductive layer; and

forming a fourth conductive layer over the second insulating layer, the fourth conductive layer overlapping a part of the oxide semiconductor layer,

wherein the fourth conductive layer overlaps the second conductive layer and the third conductive layer,

wherein the oxide semiconductor layer comprises a first region and a second region, the first region being located over the second region,

wherein the first region comprises a crystal, and a c-axis of the crystal is substantially perpendicular to the second insulating layer,

wherein the second region has a lower crystallinity than the first region, and

wherein all the metal elements included in the first region are included in the second region, and all the metal elements included in the second region are included in the first region.

2. The method for manufacturing a semiconductor device, according to claim 1, wherein a temperature of the heating is 500°

C. or higher.

3. The method for manufacturing a semiconductor device, according to claim 1, wherein the oxide semiconductor layer is formed by sputtering with the use of an In—

Ga—

Zn—

O-based target.

4. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first conductive layer over a substrate;

forming a first insulating layer over the first conductive layer;

forming an oxide semiconductor layer over the first insulating layer, the oxide semiconductor layer overlapping the first conductive layer;

heating the oxide semiconductor layer to remove at least part of hydrogen contained in the oxide semiconductor layer;

forming a second conductive layer and a third conductive layer which are in contact with the oxide semiconductor layer;

forming a second insulating layer over the oxide semiconductor layer, the second conductive layer, and the third conductive layer; and

forming a fourth conductive layer over the second insulating layer, the fourth conductive layer overlapping a part of the oxide semiconductor layer,

wherein the fourth conductive layer overlaps the second conductive layer and the third conductive layer,

wherein the oxide semiconductor layer comprises a first region and a second region, the first region being located over the second region,

wherein the first region comprises a crystal, and a c-axis of the crystal is substantially perpendicular to the second insulating layer,

wherein the second region has a lower crystallinity than the first region, and

wherein all the metal elements included in the first region are included in the second region, and all the metal elements included in the second region are included in the first region.

5. The method for manufacturing a semiconductor device, according to claim 4, wherein a temperature of the heating is 500°

C. or higher.

6. The method for manufacturing a semiconductor device, according to claim 4, wherein the oxide semiconductor layer is formed by sputtering with the use of an In—

Ga—

Zn—

O-based target.