Semiconductor device with reduced gate length

• US 8,999,805 B1
• Filed: 10/05/2013
• Issued: 04/07/2015
• Est. Priority Date: 10/05/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Colinge, Jean-Pierre, Ching, Kuo-Cheng, Guo, Ta-Pen, Diaz, Carlos H.
• Primary Examiner(s): Nhu, David
• Application Number:
  US14/046,960
• Publication Number:
  US 20150097227A1
• Time in Patent Office: 549 Days
• Field of Search: 438/311, 438/680, 438/752, 438/753, 438/762, 438/700, 438/786, 438/787, 438/791, 438/782, 257/347, 257/396, 257/E21.006, 257/E21.045, 257/E21.056, 257/E21.061, 257/E21.092, 257/E21.121, 257/E21.123, 257/E21.129, 257/E21.126, 257/E21.127, 257/E21.17, 257/E21.231, 257/E21.267, 257/E21.293, 257/E21.32
• US Class Current: 438/311
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/413 Nanosized electrodes, e.g. nanowire electrodes comprising one or a plurality of nanowires nanosized carbon materials, e.g. carbon nanotubes, per se C01B32/15; transparent electrodes comprising carbon nano-tubes H10K30/821, nanotechnology per se B82B
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate region surrounding the channel region. The gate region includes a gate electrode. A gate electrode length of the gate electrode is less than about 10 nm. A method of forming a semiconductor device is provided.

Claims

1. A semiconductor device comprising:

a first type region comprising a first conductivity type;

a second type region comprising a second conductivity type;

a channel region extending between the first type region and the second type region; and

a gate region surrounding the channel region, the gate region comprising a gate electrode, wherein a gate electrode length of the gate electrode is less than about 10 nm.

2. The semiconductor device of claim 1, comprising a first dielectric region between the gate electrode and a first portion of the first type region.

3. The semiconductor device of claim 2, wherein the first dielectric region surrounds a second portion of the first type region.

4. The semiconductor device of claim 1, wherein the first type region comprises a source region and the second type region comprises a drain region.

5. The semiconductor device of claim 1, wherein the first type region comprises a drain region and the second type region comprises a source region.

6. The semiconductor device of claim 1, wherein the first conductivity type of the first type region is the same as the second conductivity type of the second type region.

7. A method of forming a semiconductor device, the method comprising:

forming a first type region comprising a first conductivity type;

forming a second type region comprising a second conductivity type;

forming a channel region extending between the first type region and the second type region; and

forming a gate region surrounding the channel region, the gate region comprising a gate electrode, wherein a gate electrode length of the gate electrode is less than about 10 nm.

8. The method of claim 7, comprising forming vertical nanowires over a substrate region prior to forming the first type region comprising the first conductivity type.

9. The method of claim 8, comprising forming a first oxide region surrounding the vertical nanowires.

10. The method of claim 8, comprising forming a first mask portion of a first mask region over a first portion of the vertical nanowires and forming a second mask portion of the first mask region over a second portion of the vertical nanowires.

11. The method of claim 10, comprising removing a third portion of the vertical nanowires that is not covered by the first mask portion or the second mask portion of the first mask region.

12. The method of claim 10, comprising:

forming a third mask region over the second portion of the vertical nanowires and over a second portion of the substrate region; and

doping a first portion of the substrate region such that the first portion of the substrate region comprises the first conductivity type.

13. The method of claim 12, comprising:

forming a fourth mask region over the first portion of the vertical nanowires and over the first portion of the substrate region; and

doping the second portion of the substrate region such that the second portion of the substrate region comprises the second conductivity type, the second conductivity type opposite the first conductivity type.

14. The method of claim 7, comprising forming a first dielectric region on a first portion of the first type region.

15. A method of forming a semiconductor device, the method comprising:

forming a first type region comprising a first conductivity type;

forming a second type region comprising a second conductivity type;

forming a channel region extending between the first type region and the second type region;

forming a first dielectric region on a first portion of the first type region;

forming a gate electrode over the first dielectric region and surrounding the channel region, wherein a gate electrode length of the gate electrode is less than about 10 nm; and

forming a second dielectric region on the gate electrode.

16. The method of claim 15, comprising forming a silicide layer over the second dielectric region.

17. The method of claim 16, comprising annealing the silicide layer to the second type region.

18. The method of claim 16, comprising forming a second type region contact in contact with the silicide layer.

19. The method of claim 15, comprising forming a gate region contact in contact with the gate electrode.

20. The method of claim 15, comprising forming a first type region contact in contact with the first type region.