Method of making a stacked microelectronic package

• US 8,999,810 B2
• Filed: 08/19/2013
• Issued: 04/07/2015
• Est. Priority Date: 10/10/2006
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Oganesian, Vage
• Primary Examiner(s): HENRY, CALEB E
• Application Number:
  US13/970,028
• Publication Number:
  US 20130330905A1
• Time in Patent Office: 596 Days
• Field of Search: 257/678, 257/686, 438/106, 438/109, 438/110, 438/113
• US Class Current: 438/401
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/83855 Hardening the adhesive by curing, i.e. thermosetting
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A method of making a stacked microelectronic package by forming a microelectronic assembly by stacking a first subassembly including a plurality of microelectronic elements onto a second subassembly including a plurality of microelectronic elements, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements, then forming notches in the microelectronic assembly so as to expose the traces of at least some of the plurality of microelectronic elements, then forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces and dicing the assembly into packages. Additional embodiments include methods for creating stacked packages using substrates and having additional traces that extend to both the top and bottom of the package.

Claims

1. A method of manufacturing a stacked package comprising the steps of:

aligning saw lanes of a first wafer with saw lanes of a second wafer such that the saw lanes of the first wafer are positioned above the saw lanes of the second wafer, each of the first and second wafers having first and second microelectronic elements adjacent to and separated by a first saw lane of the saw lanes in a direction transverse to the first saw lane, each of the first and second microelectronic elements of each of the first and second wafers having at least a first trace extending therefrom towards the saw lanes;

exposing at least the first traces of each of the first and second microelectronic elements of each of the first and second wafers by at least partially cutting through the aligned first saw lane of the first wafer and second wafer; and

forming a lead in contact with at least the exposed first traces of each of the first and second microelectronic elements of each of the first and second wafers; and

severing the first and second wafers to form first and second individual stacked packages, each of the first and second individual stacked packages including portions of each of the first and second wafers, such that a first portion of the lead is in contact with and in electrical communication with the first traces of each of the first and second wafers of the first individual stacked package and a second portion of the lead is in contact with and in electrical communication with the first traces of each of the first and second wafers of the second individual stacked package.

2. The method of claim 1, wherein the first and second wafers include a plurality of microelectronic elements in electrical contact with the plurality of traces.

3. The method of claim 2, further comprising attaching the first wafer to the second wafer after the saw lanes of the two wafers are aligned.

4. The method of claim 2, wherein the leads include first ends that extend to a front face of one of the wafers.

5. The method of claim 4, further comprising providing solder bumps at the first ends of the leads for attaching to an additional microelectronic device.

6. The method of claim 1, further comprising aligning the saw lanes of at least one additional wafer with the saw lanes of the first and second wafers, wherein during the step of exposing the plurality of traces of the first and second wafer a plurality of traces of the at least one additional wafer is also exposed.

7. A method of making a stacked microelectronic package, the method comprising the steps of:

forming a microelectronic assembly by stacking a first subassembly having saw lanes and including a plurality of microelectronic elements onto a substrate having saw lanes such that the saw lanes of the first subassembly are aligned with the saw lanes of the substrate, stacking a second subassembly having saw lanes and including a plurality of microelectronic elements above said first subassembly such that the saw lanes of the second subassembly are aligned with the saw lanes of the first subassembly, at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly having traces that extend to respective edges of the microelectronic elements;

forming notches in the microelectronic assembly at the saw lanes of the respective subassemblies so as to expose the traces of at least some of the plurality of microelectronic elements; and

forming leads at the side walls of the notches, the leads being in electrical communication with at least some of the traces.

8. The method of claim 7, wherein a relief channel, aligned with the saw lanes of the substrate, extends partially through the substrate.

9. The method of claim 7, wherein the leads include first ends that extend to an upper face of the second subassembly.

10. The method of claim 9, wherein the leads include second ends that extend to an upper face of the substrates.

11. The method of claim 8, wherein the forming of notches does not include forming notches in the substrate.

12. The method of claim 7, further comprising dicing through the saw lanes of the substrate to form individual stacked packages.

13. The method of claim 7, wherein during the forming of the microelectronic assembly, a first face of the first subassembly is adhered to a second face of the substrate by an adhesive.

14. The method of claim 7, wherein at least some of the plurality of microelectronic elements of said first subassembly and said second subassembly have traces that extend across said saw lanes of said first subassembly and said second subassembly.

15. The method of claim 7, wherein the forming of notches includes forming initial notches in at least said first subassembly so as to expose said traces and filling said initial notches with adhesive so as to cover said traces, forming initial notches in at least said second subassembly so as to expose said traces and filling said initial notches with adhesive so as to cover said traces, and forming said notches in said adhesive so as to expose the traces of at least some of the plurality of microelectronic elements.