Method and structure of monolithically integrated ESD supperssion device

• US 8,999,835 B2
• Filed: 03/01/2012
• Issued: 04/07/2015
• Est. Priority Date: 07/28/2008
• Status: Active Grant

• Current Assignee: Movella Incorporated (Movella Holdings, Inc.)
• Original Assignee: mCube, Inc.
• Inventors: Yang, Xiao (Charles)
• Primary Examiner(s): Tran, Tony
• Application Number:
  US13/410,273
• Publication Number:
  US 20130065387A1
• Time in Patent Office: 1,132 Days
• Field of Search: 438/600, 257/E21.591
• US Class Current: 438/600
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A method of fabricating ESD suppression device includes forming conductive pillars dispersed in a dielectric material. The gaps formed between each pillar in the device behave like spark gaps when a high voltage ESD pulse occurs. When the voltage of the pulse reaches the “trigger voltage” these gaps spark over, creating a very low resistance path. In normal operation, the leakage current and the capacitance is very low, due to the physical gaps between the conductive pillars. The proposed method for fabricating an ESD suppression device includes micromachining techniques to be on-chip with device ICs.

Claims

1. A method for fabricating an electrostatic discharge device for an integrated circuit, the method comprising:

providing a semiconductor substrate;

forming a voltage discharge region overlying an inner portion of the semiconductor substrate, the forming of the voltage discharged region comprising;

forming a plurality of isolated conductive regions arranged as a vertical array, the array being numbered from 1 through N in a first direction and the array being numbered from 1 through M in a second direction;

each of me conductive regions comprising an isolated tungsten plug;

forming a dielectric material provided spatially around each of the isolated conductive regions to form a thickness of material having a surface region, wherein each of the conductive regions is physically separated from the other conductive regions by a portion of the dielectric material;

forming an input region coupled to a first region of the plurality of conductive regions;

forming an output region coupled to a second region of the plurality of conductive regions;

forming an input line overlying a first region of the semiconductor substrate region and coupled to the input region of the plurality of conductive regions;

forming an output line overlying a second region of the semiconductor substrate region and coupled to the output region of the plurality of conductive regions;

further comprising coupling the output line to a ground potential; and

wherein the dielectric material is selected from air, silicon dioxide, silicon nitride, and silicon oxynitride.

2. The method of claim 1 further comprising coupling the input line to a bond pad.

3. The method of claim 1 further comprising coupling the input line to an input pad.

4. The method of claim 1 further comprising coupling the input line to one or more integrated circuit modules.

5. The method of claim 1 further comprising coupling the output line to one or more integrated circuit modules.

6. The method of claim 1 wherein forming the plurality of conductive regions comprises forming a plurality of pillars.

7. The method of claim 1 wherein forming the plurality of conductive regions includes forming each of the plurality of conductive regions as a shape characterized by a column.

8. The method of claim 1 wherein forming the dielectric material includes separating each pair of the conductive regions by a portion of the dielectric material.

9. The method of claim 1 wherein forming the plurality of conductive regions includes forming at least two of the conductive regions separated by a predetermined gap, the gap including a portion of dielectric material therein provided a breakdown voltage between the two conductive regions.

10. The method of claim 1 wherein the array is formed in a regular pattern.

11. The method of claim 1 wherein the array is formed in an irregular pattern.

12. The method of claim 1 wherein forming the one or more of the conductive regions comprises forming a regular shape or forming the one or more of the conductive regions comprises forming an irregular shape.

13. The method of claim 1 wherein forming the voltage discharge region comprises forming the plurality of conductive regions overlying the dielectric layer.

14. The method of claim 1 wherein forming the plurality of conductive regions includes a micromachining process.

15. The method of claim 1 wherein the first direction and the second direction are parallel to the semiconductor substrate.

16. The method of claim 1 wherein the first direction and the second direction are normal to the semiconductor substrate.

17. The method of claim 1 wherein each of the plurality of conductive regions includes a pillar structure have a cross-sectional shape selected from:

a circle, a square, a pentagon, a hexagon, a star, and a hexadecagon.

18. A method for fabricating an electrostatic discharge device for an integrated circuit, the method comprising:

providing a semiconductor substrate;

forming a voltage discharge region overlying an inner portion of the semiconductor substrate, the forming of the voltage discharged region comprising;

forming a plurality of isolated conductive pillars arranged as a vertical array, the array being numbered from 1 through N in a first direction and the array being numbered from 1 through M in a second direction, each of the conductive pillars comprising an isolated tungsten plug;

forming a dielectric material provided spatially around each of the isolated conductive pillars to form a thickness of material having a surface region, wherein each of the conductive pillars is only in physical contact with the dielectric material and is physically separated from the other conductive pillars by a portion of the dielectric material;

forming an input region coupled to a first region of the plurality of conductive pillars;

forming an output region coupled to a second region of the plurality of conductive pillars;

forming an input line overlying a first region of the semiconductor substrate region and coupled to the input region of the plurality of conductive pillars and to a bond pad;

forming an output line overlying a second region of the semiconductor substrate region and coupled to the output region of the plurality of conductive pillars and to ground; and

wherein the dielectric material is selected from air, silicon dioxide, silicon nitride, and silicon oxynitride.