Semiconductor structure with substitutional boron and method for fabrication thereof

• US 8,999,861 B1
• Filed: 05/11/2012
• Issued: 04/07/2015
• Est. Priority Date: 05/11/2011
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: SuVolta, Inc.
• Inventors: Scudder, Lance, Ranade, Pushkar, Stager, Charles, Shifren, Lucian, Zhao, Dalong, Sridharan, U.C., Duane, Michael
• Primary Examiner(s): Le, Thao X
• Assistant Examiner(s): GORDON, MATTHEW E
• Application Number:
  US13/469,249
• Time in Patent Office: 1,061 Days
• Field of Search: 438/197, 438/283, 438/479, 438/202, 438/221, 438/527, 257/369, 257/377, 257/408
• US Class Current: 438/766
• CPC Class Codes: H01L 21/02205 the layer being characterised by the precursor material for deposition
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method for fabricating a semiconductor structure so as to have reduced junction leakage is disclosed. The method includes providing substitutional boron in a semiconductor substrate. The method includes preparing the substrate using a pre-amorphization implant and a carbon implant followed by a recrystallization step and a separate defect repair/activation step. Boron is introduced to the pre-amorphized region preferably by ion implantation.

Claims

1. A method for fabricating a semiconductor structure on a semiconductor substrate, comprising:

masking portions of the substrate to form a pattern of transistors;

performing a pre-amorphization implant into selected open areas defining a channel stack underlying a gate for a plurality of transistor elements of a similar type;

performing a carbon ion implantation into the selected open areas in addition to the pre-amorphization implant;

performing a boron ion implantation into the selected open areas in addition to the carbon ion implantation so as to form a screening region for the transistor element;

performing a solid phase epitaxy after the carbon and boron ion implantations to cause the amorphized portions to transform into crystalline structures;

performing an activation anneal to activate the boron by rendering the boron substitutional;

forming a threshold voltage control layer on the boron screening region of the transistor element; and

forming an epitaxial channel layer on the threshold control layer of the transistor element.

2. The method of claim 1, wherein the threshold voltage control layer is comprised of ion implanted boron.

3. The method of claim 1, wherein the threshold voltage control layer is comprised of a fully substitutional in-situ doped epitaxial layer.

4. The method of claim 1, wherein the activation anneal is a spike anneal performed at a temperature of 800°

C. to 1500°

C.

5. The method of claim 4, wherein the spike anneal is performed after the solid phase epitaxy but prior to other thermal processes performed on the semiconductor substrate.

6. The method of claim 1, wherein the pre-amorphization implant uses germanium.