Nonvolatile memory device with upper source plane and buried bit line

• US 9,000,510 B2
• Filed: 09/10/2012
• Issued: 04/07/2015
• Est. Priority Date: 12/28/2011
• Status: Expired due to Fees

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Hong, Young-Ok
• Primary Examiner(s): Montalvo, Eva Y
• Assistant Examiner(s): Dulka, John P
• Application Number:
  US13/608,652
• Publication Number:
  US 20130168757A1
• Time in Patent Office: 939 Days
• Field of Search: 257/324, 257/E29.309, 257/E21.423
• US Class Current: 257/324
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A nonvolatile memory device includes: a channel layer extending in a vertical direction from a substrate; a plurality of interlayer dielectric layers and word lines alternately stacked along the channel layer over the substrate; a bit line formed under plurality of interlayer dielectric layers and word lines, coupled to the channel layer, and extending in a direction crossing the word lines; and a common source layer coupled to the channel layer and formed over the plurality of interlayer dielectric layers and word lines.

Claims

1. A nonvolatile memory device comprising:

a channel layer extending in a vertical direction from a substrate;

a plurality of interlayer dielectric layers and word lines alternately stacked along the channel layer over the substrate;

a bit line formed under a plurality of interlayer dielectric layers and word lines, coupled to the channel layer, and extending in a direction crossing the word lines; and

a common source layer coupled to the channel layer and formed over the plurality of interlayer dielectric layers and word lines,

wherein the common source layer is divided into unit blocks by slits which are filled with an insulation layer.

2. The nonvolatile memory device of claim 1, further comprising an interlayer dielectric layer and an upper select line interposed between the word lines and the common source layer.

3. The nonvolatile memory device of claim 1, further comprising an interlayer dielectric layer and a lower select line interposed between the word lines and the bit line.

4. The nonvolatile memory device of claim 1, further comprising a memory layer interposed between the channel layer and the word lines.

5. The nonvolatile memory device of claim 1, further comprising a bit line contact plug coupled to the bit line and extending in the same direction as the channel layer.

6. The nonvolatile memory device of claim 1, wherein the bit line includes polysilicon or metal silicide.

7. The nonvolatile memory device of claim 1, wherein the common source layer includes a metal.

8. The nonvolatile memory device of claim 1, wherein the common source layer has a plate or mesh shape.