Digital tunable inter-stage matching circuit

• US 9,000,847 B2
• Filed: 09/06/2011
• Issued: 04/07/2015
• Est. Priority Date: 08/19/2009
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Zhao, Yu, Nejati, Babak, Pletcher, Nathan M, Hadjichristos, Aristotele
• Primary Examiner(s): Choe, Henry
• Application Number:
  US13/226,397
• Publication Number:
  US 20110316636A1
• Time in Patent Office: 1,309 Days
• Field of Search: 330/98, 330/150, 330/302, 330/310
• US Class Current: 330/310
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/42 Modifications of amplifiers to extend the bandwidth
• CPC Class Codes: H03F 2200/318 A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03H 7/40 Automatic matching of load impedance to source impedance

Abstract

A tunable inter-stage matching circuit that can improve performance is described. In an exemplary design, an apparatus comprises a driver amplifier and a power amplifier. The apparatus may further include an inter-stage matching circuit tunable in discrete steps for matching impedances between the driver amplifier and the power amplifier. The tunable inter-stage matching circuit may include a bank of capacitors, each capacitor of the bank coupled in series with a switch for coupling the capacitor to a ground voltage.

Claims

1. An apparatus comprising:

a driver amplifier;

a power amplifier;

an inter-stage matching circuit tunable in discrete steps for matching impedances between the driver amplifier and the power amplifier, the tunable inter-stage matching circuit including a bank of capacitors, a fixed capacitor coupled in series between the driver amplifier and the bank of capacitors, and a first inductor coupled to and in series between the power amplifier and the bank of capacitors, each capacitor of the bank coupled in series with a switch for coupling the capacitor to a ground voltage; and

a second inductor coupled between the driver amplifier and the inter-stage matching circuit and the first inductor coupled between the inter-stage matching circuit and the power amplifier.

2. The apparatus of claim 1, the inter-stage matching circuit further comprising a fixed capacitor coupled in parallel with each capacitor of the bank.

3. The apparatus of claim 1, each switch of a plurality of switches configured for coupling an associated capacitor to the ground voltage or decoupling the associated capacitor from the ground voltage based on a received control signal.

4. The apparatus of claim 1, further comprising the fixed capacitor coupled between the first inductor and the inter-stage matching circuit.

5. The apparatus of claim 1, the inter-stage matching circuit further comprising a switch coupled between the bank of capacitors and a bias voltage.

6. The apparatus of claim 1, each of the driver amplifier, the power amplifier, and the inter-stage matching circuit implemented on a common integrated circuit.

7. The apparatus of claim 2, the fixed capacitor coupled in series with the bank of switchable capacitors.

8. The apparatus of claim 2, the fixed capacitor coupled n parallel with the bank of switchable capacitors.

9. The apparatus of claim 1, each switch of a plurality of switches implemented with at least one metal oxide semiconductor (MOS) transistor.

10. The apparatus of claim 1, the bank of switchable capacitors comprising switchable capacitors having either binary weighted capacitance values or equal capacitance values.

11. The apparatus of claim 1, each capacitor of the bank of switchable capacitors coupled to a stack of one or more transistors.

12. A method, comprising:

receiving a signal from a first circuit and conveying another signal to a second circuit; and

matching an impedance between the first circuit and the second circuit with an inter-stage matching circuit tunable in discrete steps and comprising a plurality of switchable capacitors in a parallel configuration, a fixed capacitor coupled in series between the first circuit and the bank of capacitors, and a first inductor coupled to and in series between the second circuit and the plurality of switchable capacitors, each switchable capacitor configured to be coupled to a ground voltage via a switchable element, and a second inductor coupled between the first circuit and the inter-stage matching circuit and the first inductor coupled between the inter-stage matching circuit and the second circuit.

13. The method of claim 12, the matching comprising setting a tunable capacitor to one of a plurality of discrete capacitance values by controlling a plurality of switchable elements coupled to a plurality of capacitors of the tunable capacitor.

14. The method of claim 12, further comprising conveying one or more control signals to one or more switchable elements of the plurality of switchable elements for configuring the one or more switchable elements.

15. The method of claim 12, the matching comprising tuning a tunable capacitor to one of a plurality of discrete capacitance values by at least one of coupling one or more capacitors of a bank of capacitors to a ground voltage and decoupling the one or more capacitors of the bank of capacitors from the ground voltage to match an impedance between the first circuit and the second circuit.

16. The method of claim 15, the tuning comprising at least one of closing one or more switches to couple the one or more capacitors to the ground voltage or opening one or more switches to decouple the one or more capacitors from the ground voltage.

17. A device comprising:

means for receiving a signal from a first circuit and conveying another signal to a second circuit; and

means for matching an impedance between the first circuit and the second circuit with an inter-stage matching circuit tunable in discrete steps and comprising a plurality of switchable capacitors in a parallel configuration, a fixed capacitor coupled in series between the first circuit and the bank of capacitors, and a first inductor coupled to and in series between the second circuit and the plurality of switchable capacitors, each switchable capacitor configured to be coupled to a ground voltage via a switchable element, and a second inductor coupled between the first circuit and the inter-stage matching circuit and the first inductor coupled between the inter-stage matching circuit and the second circuit.

18. The device claim 17, the means for matching comprising means for tuning the tunable capacitor to one of a plurality of discrete capacitance values by at least one of coupling one or more capacitors of a bank of capacitors to a ground voltage and decoupling the one or more capacitors of the bank of capacitors from the ground voltage to match an impedance between the first circuit and the second circuit.

19. The device of claim 17, the means for matching comprising means for setting the tunable capacitor to one of a plurality of discrete capacitance values by controlling a plurality of switchable elements coupled to a plurality of capacitors of the tunable capacitor.