Ultra-wide band frequency modulator

• US 9,000,858 B2
• Filed: 06/07/2012
• Issued: 04/07/2015
• Est. Priority Date: 04/25/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Sun, Bo, Dorosenco, Alexander
• Primary Examiner(s): Johnson, Ryan
• Application Number:
  US13/490,746
• Publication Number:
  US 20130287065A1
• Time in Patent Office: 1,034 Days
• Field of Search: 332/119, 332/120, 332/127, 332/128, 332/144, 332/145, 375/302
• US Class Current: 332/144
• CPC Class Codes: H03C 3/02 Details
• CPC Class Codes: H03C 3/0941 applying frequency modulation at more than one point in the loop
• CPC Class Codes: H03C 3/095 applying frequency modulation to the loop in front of the voltage controlled oscillator
• CPC Class Codes: H03C 3/0966 modulating the reference clock
• CPC Class Codes: H03C 5/00 Amplitude modulation and angle modulation produced simultaneously or at will by the same modulating signal H03C7/00 takes precedence
• CPC Class Codes: H04L 27/2003 for continuous phase modulation frequency shift keying H04L27/10
• CPC Class Codes: H04L 27/2032 for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner

Abstract

An ultra-wide band frequency modulator is disclosed. The frequency modulator includes a direct modulation phase lock loop that receives a small component. The frequency modulator also includes a delay module that produces a plurality of delay lines. The frequency modulator further includes an edge selector that receives a large component and the plurality of delay lines.

Claims

1. An ultra-wide band frequency modulator, comprising:

a direct modulation phase lock loop that receives a small component of modulation data;

a delay module that comprises a plurality of delay lines; and

an edge selector that receives a large component of the modulation data and a plurality of delayed signals over the plurality of delay lines.

2. The frequency modulator of claim 1, wherein the small component is a phase modulation component and the large component is a phase modulation component.

3. The frequency modulator of claim 1, wherein the small component is a frequency modulation component and the large component is a frequency modulation component.

4. The frequency modulator of claim 3, wherein the small component comprises frequencies at or below 3 megahertz and the large component comprises frequencies above 3megahertz.

5. The frequency modulator of claim 1, wherein the direct modulation phase lock loop is a digital phase lock loop.

6. The frequency modulator of claim 1, wherein the small component is injected into the direct modulation phase lock loop through a two point injection.

7. The frequency modulator of claim 1, wherein the ultra-wide band frequency modulator is a polar modulator.

8. The frequency modulator of claim 1, wherein the direct modulation phase lock loop provides a phase lock loop output signal to the delay module.

9. The frequency modulator of claim 1, wherein the edge selector processes the large component and the plurality of delayed signals to produce a phase output signal.

10. A method for facilitating wireless communication in a wireless network, comprising:

processing a small component of modulation data by a direct modulation phase lock loop;

processing a large component of the modulation data by a digital frequency offset generator that comprises a delay module and an edge selector, wherein the delay module comprises a plurality of delay lines to the edge selector; and

outputting a phase output signal based on the processing of the small component and the processing of the large component.

11. The method of claim 10, further comprising:

dividing the modulation data into an amplitude component and a frequency component;

dividing the frequency component according to a threshold value to obtain the small component and the large component; and

providing the small component to the direct modulation phase lock loop and the large component to the digital frequency offset generator.

12. The method of claim 11, wherein the threshold value is 3 megahertz, wherein the small component is at or below the threshold value, and wherein the large component is above the threshold value.

13. The method of claim 10, wherein the edge selector processes the large component.

14. The method of claim 10, further comprising:

providing a direct modulation phase lock loop output to the delay module;

processing the direct modulation phase lock loop output using the delay module to obtain a plurality of delayed signals; and

providing the plurality of delayed signals to the edge selector over the plurality of delay lines.

15. The method of claim 14, wherein the edge selector processes the large component and the plurality of delayed signals.

16. The method of claim 10, wherein the small component is a phase modulation component and the large component is a phase modulation component.

17. The method of claim 10, wherein the small component is a frequency modulation component and wherein the large component is a frequency modulation component.

18. The method of claim 10, wherein the direct modulation phase lock loop is a digital phase lock loop.

19. The method of claim 10, wherein the small component is injected into the direct modulation phase lock loop through a two point injection.

20. The method of claim 10, wherein the method is performed by a wireless device that comprises an ultra-wide band frequency modulator.

21. The method of claim 20, wherein the ultra-wide band frequency modulator comprises:

the direct modulation phase lock loop;

the delay module; and

the edge selector.

22. The method of claim 20, wherein the ultra-wide band frequency modulator is a polar modulator.

23. An apparatus for facilitating wireless communications in a wireless network, comprising:

means for processing a small component of modulation data by a direct modulation phase lock loop;

means for processing a large component of the modulation data by a digital frequency offset generator that comprises a delay module and an edge selector, wherein the delay module comprises a plurality of delay lines to the edge selector; and

means for outputting a phase signal based on the processing of the small component and the processing of the large component.

24. The apparatus of claim 23, further comprising:

means for dividing the modulation data into an amplitude component and a frequency component;

means for dividing the frequency component according to a threshold value to obtain the small component and the large component; and

means for providing the small component to the direct modulation phase lock loop and the large component to the digital frequency offset generator.

25. The apparatus of claim 23, further comprising:

means for providing a direct modulation phase lock loop output to the delay module;

means for processing the direct modulation phase lock loop output using the delay module to obtain a plurality of delayed signals; and

means for providing the plurality of delayed signals to the edge selector over the plurality of delay lines.