Gen II meter system with multiple processors, multiple detection sensor types, fault tolerance methods, power sharing and multiple user interface methods
First Claim
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1. A parking space monitoring system for handling various parking space management, comprising:
- a node with a piece of electronic equipment;
a plurality of microprocessors located within the same piece of electronic equipment of the node, wherein individual ones of microprocessors are configured to monitor and respond to various parking space management conditions of the parking space monitoring system;
a power control mechanism configured to reinitialize individual ones of said microprocessors without affecting an operation of the other of said microprocessors; and
wherein an individual operability status of the individual ones of said microprocessors is queried by another of said microprocessors and instructs said power control mechanism to reinitialize a non-responsive microprocessor.
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Abstract
A parking space monitoring system, with multiple microprocessors for handling various parking space management conditions, including at least one of the following conditions: (1) Space Occupancy (vehicle detection); (2) Parking Meter Status; (3) Display of Parking Policy to Motorists; (3) Motorist User Interactions; (4) Maintenance User Interactions; (5) Radio Communications with a Central management system and Network; and (6) Coordination of the operation between various ones of the microprocessors.
64 Citations
13 Claims
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1. A parking space monitoring system for handling various parking space management, comprising:
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a node with a piece of electronic equipment; a plurality of microprocessors located within the same piece of electronic equipment of the node, wherein individual ones of microprocessors are configured to monitor and respond to various parking space management conditions of the parking space monitoring system; a power control mechanism configured to reinitialize individual ones of said microprocessors without affecting an operation of the other of said microprocessors; and wherein an individual operability status of the individual ones of said microprocessors is queried by another of said microprocessors and instructs said power control mechanism to reinitialize a non-responsive microprocessor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification