Complex passive design with special via implementation

• US 9,001,031 B2
• Filed: 07/30/2012
• Issued: 04/07/2015
• Est. Priority Date: 07/30/2012
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Lo, Chi Shun, Lan, Je-Hsiung Jeffrey, Velez, Mario Francisco, Mikulka, Robert Paul, Zuo, Chengjie, Yun, Changhan Hobie, Kim, Jonghae
• Primary Examiner(s): Moorad, Waseem
• Application Number:
  US13/562,168
• Publication Number:
  US 20140028543A1
• Time in Patent Office: 981 Days
• Field of Search: 345/156, 336/200, 361/679.21, 427/58, 427/123, 216/18
• US Class Current: 345/156
• CPC Class Codes: G02B 26/001 based on interference in an adjustable optical cavity interference filters G02B5/28; devices or arrangements using multiple reflections in spectrometry or monochromators G01J3/26
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces.

Claims

1. An integrated passive device, comprising:

a substrate;

a first conductive trace over the substrate;

a second conductive trace over the first conductive trace; and

an interlayer dielectric between a portion of the first conductive trace and the second conductive trace to electrically isolate the first conductive trace from the second conductive trace, the interlayer dielectric having a hole, the hole being at least partially filled and defining a via to provide direct electrical connection between the conductive traces, wherein a width of the hole is greater than a width of each of the conductive traces, both widths being lateral dimensions of the device.

2. The device of claim 1, wherein the width of the hole laterally extends beyond the edges of the conductive traces.

3. The device of claim 1, wherein the second conductive trace includes copper.

4. The device of claim 1, wherein a thickness of the second conductive trace is greater than about 1 μ

m.

5. The device of claim 1, wherein a thickness of the interlayer dielectric is between about 1 μ

m and about 5 μ

m.

6. The device of claim 1, wherein the second conductive trace forms part of a magnetic domain passive component.

7. The device of claim 6, wherein the magnetic domain passive component is one of an inductor, transformer and a passive filter.

8. The device of claim 1, wherein the second conductive trace is directly over and in contact with at least a portion of the first conductive trace not in contact with the interlayer dielectric.

9. The device of claim 1, wherein the width of the hole is greater than five times the width of at least one of the conductive traces.

10. The device of claim 1, wherein the first conductive trace includes at least aluminum or an aluminum alloy.

11. The device of claim 1, further comprising a second interlayer dielectric over the second conductive trace, wherein the hole is at least partially filled by the second interlayer dielectric and the second conductive trace.

12. The device of claim 1, further comprising:

a display;

a processor that is configured to communicate with the display, the processor being configured to process image data; and

a memory device that is configured to communicate with the processor.

13. The device of claim 12, further comprising:

a driver circuit configured to send at least one signal to the display; and

a controller configured to send at least a portion of the image data to the driver circuit.

14. The device of claim 12, further comprising:

an image source module configured to send the image data to the processor, wherein the image source module includes at least one of a receiver, transceiver, and transmitter.

15. The device of claim 12, further comprising:

an input device configured to receive input data and to communicate the input data to the processor.

16. An integrated passive device, comprising:

a substrate;

first means for conducting electricity, positioned over the substrate;

second means for conducting electricity, positioned over the first conducting means;

means for electrically isolating the first conducting means and the second conducting means, positioned between a portion of the first conducting means and the second conducting means; and

means for providing electrical connection in the electrically isolating means between the first conducting means and the second conducting means, wherein the means for providing electrical connection is defined by a hole in the electrically isolating means, the hole being at least partially filled by the second conducting means, and wherein a width of the hole is greater than a width of each of the first conducting means and the second conducting means, both widths being lateral dimensions of the device.

17. The device of claim 16, wherein the hole has a width that laterally extends beyond the edges of each of the first conducting means and the second conducting means.

18. The device of claim 16, wherein the second conducting means includes copper.

19. The device of claim 16, wherein a thickness of the second conducting means is greater than about 1 μ

m.

20. The device of claim 16, wherein the second conducting means forms part of a magnetic domain passive component.

21. The device of claim 16, further comprising a sec-end means for providing electrical insulation over the second conducting means.

22. A method of manufacturing an integrated passive device, comprising:

providing a substrate;

depositing a first conductive trace over the substrate;

depositing a first interlayer dielectric over the first conductive trace;

forming a hole in the first interlayer dielectric, wherein a width of the hole is greater than a width of the first conductive trace, the hole defining a via for electrical interconnection between conductive traces;

depositing a second conductive trace in the hole over the first conductive trace to form the via, wherein the width of the hole is greater than a width of the second conductive trace, both widths being lateral dimensions of the device; and

depositing a second interlayer dielectric over the second conductive trace.

23. The method of claim 22, wherein forming the hole includes etching the first interlayer dielectric to expose at least a substantial portion of the first conductive trace.

24. The method of claim 23, wherein etching the first interlayer dielectric includes removing the substantial portion of the first interlayer dielectric except for one or more remaining portions of the first interlayer dielectric between the first conductive trace and the second conductive trace, wherein the one or more remaining portions of the first interlayer dielectric electrically isolate a portion of the first conductive trace from second conductive trace.

25. The method of claim 22, wherein depositing the second conductive trace and depositing the second interlayer dielectric substantially fills the hole to form the via between the conductive traces.

26. The method of claim 22, wherein depositing the second conductive trace includes electroplating copper over the first conductive trace.

27. The method of claim 22, wherein the second interlayer dielectric includes dielectric material with a thickness between about 1 μ

m and about 15 μ

m as measured from the top surface of the second conductive trace.

28. The method of claim 22, wherein the second conductive trace includes electrically conductive material with a thickness greater than about 1 μ

m.

29. The method of claim 22, wherein depositing the second conductive trace and the second interlayer dielectric occur under coarse process control constraints.

30. The method of claim 29, wherein depositing the second conductive trace and the second interlayer dielectric occur in a far back-end-of-line (FBEOL) process.

31. The method of claim 22, wherein depositing the first conductive trace includes depositing at least an aluminum or aluminum alloy over the substrate.

32. The method of claim 22, wherein the second conductive trace forms part of a magnetic domain passive component.

33. The method of claim 22, wherein the magnetic domain passive component is one of an inductor, transformer, or passive filter.

34. An integrated passive device produced by the method as recited by claim 22.