Method for driving semiconductor device

• US 9,001,566 B2
• Filed: 02/21/2014
• Issued: 04/07/2015
• Est. Priority Date: 11/06/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): YOHA, CONNIE C
• Application Number:
  US14/186,005
• Publication Number:
  US 20140169100A1
• Time in Patent Office: 410 Days
• Field of Search: 365/149, 365/72, 365/63, 365/145
• US Class Current: 365/149
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/263 Amorphous materials
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/70 : the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

Claims

1. A method for driving a semiconductor device comprising:

a first line;

a second line;

a third line;

a plurality of memory cells connected in series between the first line and the second line;

a first circuit electrically connected to the third line; and

a second circuit electrically connected to the second line,

the method comprising a writing step and a reading step, the writing step comprising steps of;

selecting one of a plurality of writing potentials; and

outputting the one of the plurality of writing potentials to the third line, and

the reading step comprising a step of;

supplying a potential to the first line; and

comparing a potential of the second line and a plurality of reference potentials,

wherein each of the plurality of memory cells comprises;

a first transistor including a first gate, a first source, and a first drain;

a second transistor including a second gate, a second source, and a second drain; and

a third transistor including a third gate, a third source, and a third drain,

wherein the second transistor includes a channel formation region comprising an oxide semiconductor, and

wherein the first gate and one of the second source and the second drain are electrically connected to each other,

wherein the first line, the first source, and the third source are electrically connected to one another,

wherein the second line, the first drain, and the third drain are electrically connected to one another, and

wherein the third line and the other of the second source and the second drain are electrically connected to each other.

2. The method for driving the semiconductor device according to claim 1,

wherein the semiconductor device further comprises a third circuit electrically connected to the first circuit and the second circuit,

wherein in the writing step, the third circuit generates the plurality of writing potentials and supplies the plurality of writing potentials to the first circuit, and

wherein in the reading step, the third circuit generates the plurality of reference potentials and supplies the plurality of reference potentials to the second circuit.

3. The method for driving the semiconductor device according to claim 1,

wherein each of the plurality of memory cells further comprises a capacitor comprising a pair of electrodes, and

wherein one of the pair of electrodes of the capacitor is electrically connected to the first gate and the one of the second source and the second drain.

4. The method for driving the semiconductor device according to claim 1, wherein each of the first transistor and the third transistor includes a channel formation region comprising a semiconductor material other than the oxide semiconductor.

5. The method for driving the semiconductor device according to claim 1, wherein each of the first transistor and the third transistor includes a channel formation region comprising silicon.

6. The method for driving the semiconductor device according to claim 1, wherein the oxide semiconductor contains In, Ga and Zn.

7. The method for driving the semiconductor device according to claim 1, wherein off-state current of the second transistor is less than or equal to 1×

10<sup>−

13</sup> A.

8. A method for driving a semiconductor device comprising:

a first line;

a second line;

a third line;

a plurality of memory cells connected in series between the first line and the second line;

a first circuit electrically connected to the third line;

a second circuit electrically connected to the second line; and

a third circuit,

the method comprising a writing step and a reading step, the writing step comprising steps of;

selecting one of a plurality of writing potentials; and

outputting the one of the plurality of writing potentials to the third line, and

the reading step comprising a step of;

selecting one of the plurality of memory cells by supplying one of a plurality of reference potentials from the third circuit; and

detecting conductance between the first line and the second line,

wherein each of the plurality of memory cells comprises;

a first transistor having a first gate, a first source, and a first drain;

a second transistor having a second gate, a second source, and a second drain; and

a capacitor comprising a pair of electrodes,

wherein the second transistor includes a channel formation region comprising an oxide semiconductor, and

wherein the first gate, one of the second source and the second drain, and one of the pair of electrodes of the capacitor are electrically connected to one another,

wherein the first line and the first source are electrically connected to each other,

wherein the second line and the first drain are electrically connected to each other,

wherein the third line and the other of the second source and the second drain are electrically connected to each other, and

wherein each of the second gate and the other of the pair of electrodes of the capacitor is electrically connected to the third circuit.

9. The method for driving the semiconductor device according to claim 8,

wherein the semiconductor device further comprises a fourth circuit electrically connected to the first circuit, the second circuit and the third circuit,

wherein in the writing step, the fourth circuit generates the plurality of writing potentials and supplies the plurality of writing potentials to the first circuit, and

wherein in the reading step, the fourth circuit generates the plurality of reference potentials and supplies the plurality of reference potentials to the second circuit and the third circuit.

10. The method for driving the semiconductor device according to claim 8, wherein the first transistor includes a channel formation region comprising a semiconductor material other than the oxide semiconductor.

11. The method for driving the semiconductor device according to claim 8, wherein the first transistor includes a channel formation region comprising silicon.

12. The method for driving the semiconductor device according to claim 8, wherein the oxide semiconductor contains In, Ga and Zn.

13. The method for driving the semiconductor device according to claim 8, wherein off-state current of the second transistor is less than or equal to 1×

10<sup>−

13</sup> A.

14. A method for driving a semiconductor device comprising:

a first line;

a second line;

a third line;

a plurality of memory cells connected in series;

a first transistor comprising a first gate and electrically connected between the first line and the plurality of memory cells;

a second transistor comprising a second gate and electrically connected between the first line and the plurality of memory cells;

a first circuit electrically connected to the third line; and

a second circuit electrically connected to the second line,

the method comprising a writing step and a reading step, the writing step comprising steps of;

selecting one of a plurality of writing potentials; and

outputting the one of the plurality of writing potentials to the third line, and

the reading step comprising a step of;

supplying a first potential to the first gate and the second gate to turn on the first transistor and the second transistor,

wherein each of the plurality of memory cells comprises;

a third transistor including a third gate, a third source, and a third drain;

a fourth transistor including a fourth gate, a fourth source, and a fourth drain; and

wherein the fourth transistor includes a channel formation region comprising an oxide semiconductor, and

wherein the third gate and one of the fourth source and the fourth drain are electrically connected to each other,

wherein the first line and the third source are electrically connected to each other through the first transistor,

wherein the second line and the third drain are electrically connected to each other through the second transistor, and

wherein the third line and the other of the fourth source are electrically connected to each other.

15. The method for driving the semiconductor device according to claim 14,

wherein each of the plurality of memory cells further comprises a fifth transistor comprising a fifth gate, a fifth source and a fifth drain,

wherein the fifth source is electrically connected to the third source,

wherein the fifth drain is electrically connected to the third drain, and

wherein the reading step further comprises steps of:

supplying a second potential to the first line; and

comparing a potential of the second line and a plurality of reference potentials.

16. The method for driving the semiconductor device according to claim 14,

wherein the semiconductor device further comprises a third circuit,

wherein each of the plurality of memory cells further comprises a capacitor comprising a pair of electrodes,

wherein the third gate, one of the fourth source and the fourth drain, and one of the pair of electrodes of the capacitor are electrically connected to one another,

wherein the other of the pair of electrodes of the capacitor is electrically connected to the third circuit, and

wherein the reading step further comprises steps of:

selecting one of the plurality of memory cells by supplying one of a plurality of reference potentials from the third circuit; and

detecting conductance between the first line and the second line.

17. The method for driving the semiconductor device according to claim 14, wherein the third transistor includes a channel formation region comprising a semiconductor material other than the oxide semiconductor.

18. The method for driving the semiconductor device according to claim 14, wherein the third transistor includes a channel formation region comprising silicon.

19. The method for driving the semiconductor device according to claim 14, wherein the oxide semiconductor contains In, Ga and Zn.

20. The method for driving the semiconductor device according to claim 14, wherein off-state current of the fourth transistor is less than or equal to 1×

10<sup>−

13</sup> A.