Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

• US 9,001,581 B2
• Filed: 02/11/2014
• Issued: 04/07/2015
• Est. Priority Date: 11/29/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US14/177,819
• Publication Number:
  US 20140159156A1
• Time in Patent Office: 420 Days
• Field of Search: 365/185.05, 365/185.26
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/34 using semiconductor devices
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 the transistor being a FinFET
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

Claims

1. A semiconductor memory device comprising:

a plurality of semiconductor memory cells;

at least one contact configured to electrically connect said memory cells to at least one control line, wherein the number of said contacts is less than the number of said memory cells; and

said memory device being configured to perform at least one of;

injecting charge into or extracting charge out of a portion of at least one of said memory cells to maintain a state of said at least one memory cell.

2. The semiconductor memory device of claim 1, wherein said semiconductor memory device is configured to perform said at least one of:

injecting charge into or extracting charge out of a portion of at least two of said memory cells to simultaneously maintain a state of each of said at least two memory cells.

3. The semiconductor memory device of claim 2, wherein said at least one of said semiconductor memory devices each comprise a floating body region configured to store data as charge therein to define said state of said memory cell;

and a back bias region configured to perform said at least one of injecting charge into or extracting charge out of said portion; and

wherein said floating body region comprises said portion.

4. The semiconductor memory device of claim 2, wherein all but at most two of said semiconductor memory devices each comprise a floating body region configured to store data as charge therein to define said state of said memory cell;

and a back bias region configured to perform said at least one of injecting charge into or extracting charge out of said portion; and

wherein said floating body region comprises said portion.

5. The semiconductor memory device of claim 1, wherein said plurality of semiconductor memory cells are connected in series.

6. The semiconductor memory device of claim 1, wherein said plurality of semiconductor memory cells are connected in parallel.

7. The semiconductor memory device of claim 1, wherein said at least one of said memory cells is configured to store multi-bit data.

8. The semiconductor memory device of claim 2, wherein said at least one of said memory cells are each configured to store multi-bit data.

9. The semiconductor memory device of claim 1, wherein said at least one of said memory cells comprises a fin-type, three-dimensional semiconductor memory cell.

10. A semiconductor memory device comprising:

a plurality of semiconductor memory cells;

a first contact configured to electrically connect said memory cells to a first control line;

a second contact configured to electrically connect said semiconductor memory cells to a second control line;

the plurality of semiconductor memory cells being directly connected to one another so that at least one of said semiconductor memory cells is not directly connected to said contacts; and

at least one of said semiconductor memory cells each comprising;

a floating body region configured to store data as charge therein to define a state of said semiconductor memory cell.

11. The semiconductor memory device of claim 10, wherein said at least one of said semiconductor memory cells each further comprise a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of said semiconductor memory cell.

12. The semiconductor memory device of claim 10, wherein said plurality of semiconductor memory cells are connected in series.

13. The semiconductor memory device of claim 10, wherein said plurality of semiconductor memory cells are connected in parallel.

14. The semiconductor memory device of claim 10, wherein said at least one of said semiconductor memory cells are each configured to store multi-bit data.

15. The semiconductor memory device of claim 10, wherein said at least one of said memory cells each comprise a fin-type, three-dimensional semiconductor memory cell.

16. A semiconductor memory device comprising at least two semiconductor memory cells, wherein at least one of said semiconductor memory cells is a contactless semiconductor memory cell, wherein said contactless semiconductor memory cell comprises a floating body region configured to store data as charge therein to define a state of said contactless semiconductor memory cell.

17. The semiconductor memory device of claim 16, wherein said at least one contactless semiconductor memory cell is configured to perform at least one of :

injecting charge into or extracting charge out of a portion of said contactless semiconductor memory cells to simultaneously maintain a state of each of said contactless semiconductor memory cells.

18. The semiconductor memory device of claim 17, wherein said at least one contactless semiconductor memory cell each comprises a floating body region configured to store data as charge therein to define said state of said contactless semiconductor memory cell;

and a back bias region configured to perform said at least one of injecting charge into or extracting charge out of a portion of said floating body region.

19. The semiconductor memory device of claim 16, wherein said at least two semiconductor memory cells comprise a plurality of said contactless semiconductor memory cells connected in series.

20. The semiconductor memory device of claim 16, wherein said at least one contactless semiconductor memory cell comprises a fin-type, three-dimensional semiconductor memory cell.