On-chip HV and LV capacitors acting as the second back-up supplies for NVSRAM auto-store operation

• US 9,001,583 B2
• Filed: 10/14/2013
• Issued: 04/07/2015
• Est. Priority Date: 10/15/2012
• Status: Active Grant

• Current Assignee: Aplus Flash Technology, Inc.
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Lee, Peter Wung, Tsao, Hsing-Ya
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US14/053,549
• Publication Number:
  US 20140104946A1
• Time in Patent Office: 540 Days
• Field of Search: 365/185.08, 365/154, 365/229
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/141 Battery and back-up supplies

Abstract

Two on-chip capacitors including one HV capacitor VPPcap and one LV VCC capacitor VCCcap are built over a NVSRAM memory chip as a back-up second power supplies for each NVSRAM cell, regardless of 1-poly, 2-poly, PMOS or NMOS flash cell structures therein. The on-chip HV and LV capacitors are preferably made from one or more MIM or MIP layers for achieving required capacitance. A simplified VCC power system circuit without a need of a State machine designed for performing only one NVSRAM Program operation without Erase operations is proposed for initiating NVSRAM'"'"'s Auto-Store operation without using any off-chip Vbat and Vcap. During the Auto-Store operation, all HV pumps and oscillators associated with the two on-chip capacitors are shut off once VCC voltage drop is detected by a VCC detector to be below 80% of regular VDD level.

Claims

1. On-chip capacitors for positive high-voltage (HV) and low-voltage (LV) back-up power supply of a NVSRAM memory, the on-chip capacitors comprising:

a first conductive material formed on top of a NVSRAM memory chip, the NVSRAM memory chip including a VDD-power pin drawing a regular VCC power to a LV PMOS device connected to a LV NMOS device and to a HV charge pump device connected to a HV PMOS device, the first conductive material being coupled to a grounded source node of the LV NMOS device;

a first insulation material isolated entirely the first conductive material;

a second conductive material formed overlying at least a part of the first insulation material, the second conductive material including a first portion and a second portion separated by another part of the first insulation material, the first portion of the second conductive material being coupled to a drain node of the LV NMOS device connected to a source node of the LV PMOS device, the second portion of the second conductive material being coupled to an output node of the HV charge pump device connected to a drain node of the HV PMOS device;

wherein the first conductive material, the first insulation material, and the first portion of the second conductive material form a first on-chip capacitor being charged from the regular VCC power through the VDD-power pin with the LV PMOS device in conduction state and the LV NMOS device in non-conduction state;

wherein the first conductive material, the first insulation material, and the second portion of the second conductive material form a second on-chip capacitor being charged from the output node of the HV charge pump device with the HV PMOS device in non-conduction state.

2. The on-chip capacitors of claim 1 wherein the NVSRAM memory chip comprises an array of NVSRAM cells, each NVSRAM cell comprises a SRAM cell coupled to a Flash cell having at least a pair of flash transistors made by either 2-poly NMOS floating-gate transistors, a 1-poly SONOS or MONOS charge-trap transistors, or a 2-poly PMOS floating gate transistors.

3. The on-chip capacitors of claim 1 wherein the first conductive material is either a metal material or a polysilicon material formed on entire layout area above a top metal layer of the NVSRAM memory chip isolated by a part of the first insulator material.

4. The on-chip capacitors of claim 1 wherein the first portion of the second conductive material and the second portion of the second conductive material are formed on substantially a same level over the first conductive material with a part of the first insulation material in between, the second conductive material being either a metal material or a polysilicon material.

5. The on-chip capacitors of claim 1 wherein the first portion of the second conductive material is formed on entire layout area above a top metal layer of the NVSRAM memory chip isolated by a part of the first insulation material and under the first conductive material with another part of the first insulation material in between, and the second portion of the second conductive material is formed over the first conductive material with yet another part of the first insulation material in between.

6. The on-chip capacitors of claim 1 further comprising one or more third conductive materials and one or more fourth conductive materials isolated by one or more second insulation materials formed entirely overlying the second conductive material formed overlying at least a part of the first insulation material overlying the first conductive material, the one or more third conductive materials being electrically coupled to the first conductive material being grounded, and the one or more fourth conductive materials including two electrically isolated portions respectively coupled electrically to the first portion and the second portion of the second conductive material for enhancing the first on-chip capacitor from a first capacitance to a second capacitance and enhancing the second on-chip capacitor from a third capacitance to a fourth capacitance.

7. The on-chip capacitors of claim 2 wherein the first on-chip capacitor is charged all time up to a VDD level whenever the regular VCC power at the VDD-power pin is stably supplied with the VDD level for operating the NVSRAM memory chip.

8. The on-chip capacitors of claim 7 wherein the first on-chip capacitor being charged all time is ready for providing a LV back-up power up to the VDD level whenever a power-loss state is detected as the VCC power at the VDD-power pin drops below 80% of the VDD level.

9. The on-chip capacitors of claim 8 wherein the LV back-up power up to the VDD level is provided to each SRAM cell and optionally to a control gate of select transistors between the SRAM cell and corresponding Flash cell in the NVSRAM memory chip for initiating in an Auto-Store operation to program a logic data in the SRAM cell to the corresponding Flash cell.

10. The on-chip capacitors of claim 2 wherein the second on-chip capacitor is constantly charged to a HV from the HV charge pump device that is refreshed at a selected frequency by an oscillator powered by the regular VCC power from the VDD-power pin, the HV being substantially a positive VPP voltage sufficient for operating NVSRAM program and erase operation.

11. The on-chip capacitors of claim 10 wherein the selected frequency is in a range of 0.2-1 Mhz or lower for consuming less than 10 μ

A VCC current from the VDD-power pin for any regular NVSRAM operations without need a high voltage.

12. The on-chip capacitors of claim 10 wherein the selected frequency is in a range of 2-10 Mhz for perform regular NVSRAM program and erase operation in about 5 ms.

13. The on-chip capacitors of claim 10 wherein the selected frequency is zero to stop the HV charge pump device whenever a power-loss state is detected as the VCC power at the VDD-power pin drops below 80% of the VDD level.

14. The on-chip capacitors of claim 13 wherein the second on-chip capacitor is ready at the power-loss state for providing a HV back-up power up to the positive VPP voltage through the HV PMOS device coupled to a word line of corresponding Flash cell.

15. The on-chip capacitors of claim 14 wherein the positive VPP voltage is about +15V or greater for increasing/decreasing Flash cell threshold level during a store operation under FN-channel scheme without erase operation, provided that each Flash cell in the NVSRAM memory chip is made by HV 2-poly floating-gate NMOS/PMOS transistors.

16. The on-chip capacitors of claim 14 wherein the positive VPP voltage is about +10V or greater for increasing Flash cell threshold level during a store operation under FN-channel scheme without erase operation, provided that each Flash cell in the NVSRAM memory chip is made by HV 1-poly charge-trapping SONOS or MONOS transistors.

17. A method for performing an auto-store operation of a NVSRAM memory chip at a power-loss state, the method comprising:

providing a low-voltage (LV) capacitor and a high-voltage (HV) capacitor formed on-chip over a NVSRAM memory chip including array of NVSRAM cells, each NVSRAM cell being made by a SRAM cell having two nodes respectively coupled to one paired Flash cell;

charging the LV capacitor to retain up to a VDD level by coupling to a VCC power line connected to a regular VDD power supply;

charging the HV capacitor to retain a VPP level by connecting to a positive HV charge pump circuit powered via the VCC power line;

determining a power-loss state associated with the NVSRAM memory chip if the VCC power line connected to the regular VDD power supply is detected to drop below 80% of the VDD level;

switching the VCC power line to the LV capacitor as a back-up power of up to the VDD level to operate each SRAM cell based on the determined power-loss state;

applying the charged VPP level at the HV capacitor to a word line of each paired Flash cell corresponding to each SRAM cell based on the determined power-loss state, the VPP level being at least higher than a programming voltage required for inducing a FN-channel effect to write each SRAM cell logic data in the two nodes into the corresponding paired Flash cell without using any off-chip capacitors and batteries.

18. The method of claim 17 wherein providing the LV capacitor and the HV capacitor comprises adding one or more metal-insulator-metal (MIM) layers overlying exiting top metal layer for the NVSRAM memory chip with an necessary thickness of insulation material in between.

19. The method of claim 17 wherein charging the LV capacitor comprises maintaining the VDD level all time whenever the power-off state is not detected by the VCC detector.

20. The method of claim 17 wherein switching the regular VCC power line to the LV capacitor based on the determined power-loss state comprises disconnecting the SRAM cell from the regular VCC power line, connecting from the two nodes of each SRAM cell to corresponding paired Flash cell to be conductive, and disconnecting the paired Flash cell to flash source lines.

21. The method of claim 17 wherein charging the HV capacitor comprises retaining the VPP level constantly by refreshing the positive HV charge pump circuit with a selected frequency set by an oscillator powered by the regular VDD power supply through the VCC power line.

22. The method of claim 21 wherein the selected frequency during regular SRAM operations without need of HV is set to 1/10 or smaller of a nominal pump frequency for other operations of the NVSRAM memory chip that need HV.

23. The method of claim 21 wherein applying the charged VPP level based on the determined power-loss state further comprises stopping the charge pump circuit and the oscillator with the selected frequency set to zero.

24. The method of claim 23 wherein the charged VPP level is at least +15V ready for increasing/decreasing threshold levels of each paired Flash cell made by HV 2-poly floating-gate NMOS/PMOS transistors for operating a NVSRAM store operation under a FN-channel scheme without erase operation.

25. The method of claim 23 wherein the charged VPP level is at least +10V ready for increasing threshold levels of each paired Flash cell made by HV 1-poly charge-trapping SONOS/MONOS transistors for operating a NVSRAM store operation under a FN-channel scheme without erase operation.

26. A VCC power system for operating an Auto-Store task of a NVSRAM memory chip, the VCC power system comprising:

a VCC power line connected to an off-chip power supply normally for providing a VDD voltage to a NVSRAM memory chip including array of NVSRAM cells each made by a SRAM cell coupled to a paired Flash cell via at least one paired select transistor;

a first on-chip capacitor formed on the NVSRAM memory chip, the first on-chip capacitor being charged up to the VDD voltage directly from the VCC power line;

a second on-chip capacitor formed on the NVSRAM memory chip next to the first on-chip capacitor, the second on-chip capacitor being charged to a positive VPP voltage from an output of a high voltage (HV) pump device powered from the VCC power line;

a VCC-level shifter including a first input connected to the VCC power line, a second input connected to the second on-chip capacitor, and a third input connected to a VCC detector configured to detect a power-loss state when voltage in the VCC power line drops below 80% of the VDD voltage;

a VPP-level shifter sharing the first input, the second input, and the third input with the VCC-level shifter and additionally including a fourth input connected to both the second on-chip capacitor and the HV pump device;

a VCC switch sharing the first input, the second input, and the third input with the VCC-level shifter;

wherein the power-loss state automatically initiates switching from the first input to the second input for providing the charged VDD voltage from the first on-chip capacitor through the VCC switch to power each SRAM cell in the NVSRAM memory chip and through the VCC-level shifter to make at least the paired select transistor in conduction state connecting each SRAM cell to the corresponding paired Flash cell, and automatically applies the positive VPP voltage from the second on-chip capacitor through the VPP-level shifter to a global word line of the corresponding paired Flash cell to initiate a store operation for writing logic data of each SRAM cell into the corresponding paired Flash cell under a FN-channel scheme without erase operation.

27. The VCC power system of claim 26 wherein each NVSRAM cell is selected from a 12-transistor NVSRAM cell having one 6-transistor SRAM cell coupled to at least one paired flash transistor in one 6-transistor Flash cell and a 10-transistor NVSRAM cell having one 6-transistor SRAM cell coupled to at least one paired flash transistor in one 4-transistor Flash cell.

28. The VCC power system of claim 27 wherein each of the at least one paired flash transistor is selected from a 2-poly floating-gate NMOS transistor, a 2-poly floating-gate PMOS transistor, a 1-poly charge-trapping SONOS or MONOS transistor.

29. The VCC power system of claim 26 wherein the first on-chip capacitor and the second on-chip capacitor are formed with an flexibility of increasing respective capacitances by adding one or more Metal-insulator-metal (MIM) layers shielded from existing top metal layer used for the VCC power line and connections to the HV pump device of the NVSRAM memory chip.

30. The VCC power system of claim 26 further comprising a low-frequency oscillator configured to set a frequency to refresh the HV pump device for charging the second on-chip capacitor to the positive VPP voltage.

31. The VCC power system of claim 30 wherein the frequency is in a range of 2.0 to 10 Mhz with the regular off-chip power supply providing the VDD voltage for fast program operation within 5 ms, the frequency is reduced to a range of 0.2 to 1 Mhz or lower during normal SRAM operation without need any high-voltage, and the frequency is set to zero once the power-loss state is detected by the VCC detector.

32. The VCC power system of claim 26 wherein the power-loss state further initiates disabling the HV pump device, disconnecting the VCC power line from each SRAM cell, making each paired select transistor in conduction state between the SRAM cell and the corresponding paired Flash cell, and disconnecting the paired Flash cell to corresponding source lines.

33. The VCC power system of claim 26 wherein the charged positive VPP voltage is at least +15V applied to the global word line of each paired Flash cell in the NVSRAM memory chip for increasing/decreasing threshold levels of the corresponding paired Flash cell made by 2-poly floating-gate NMOS/PMOS transistors during a store operation under FN-channel scheme without any erase operation.

34. The VCC power system of claim 26 wherein the charged positive VPP voltage is at least +10V applied to the global word line of each paired Flash cell in the NVSRAM memory chip for increasing threshold levels of the corresponding paired Flash cell made by 1-poly charge-trapping SONOS/MONOS transistors during a store operation under FN-channel scheme without any erase operation.

35. The VCC power system of claim 26 further comprising a negative HV pump device connected to the global flash word line of each paired Flash cell with the regular off-chip power supply providing the VDD voltage for providing a negative VNN voltage to perform a regular NVSRAM erase operation, the negative HV pump device being connected to the VPP-level shifter that contains only HV PMOS devices.