Clock synthesis systems, circuits and methods

• US 9,002,488 B2
• Filed: 12/29/2010
• Issued: 04/07/2015
• Est. Priority Date: 02/22/2010
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Castor-Perry, Kendall
• Primary Examiner(s): Tsang, Fan
• Assistant Examiner(s): Zhao, Eugene
• Application Number:
  US12/981,265
• Publication Number:
  US 20110208329A1
• Time in Patent Office: 1,560 Days
• Field of Search: 700/94, 331/4, 331/1.A, 327/156, 327/117, 375/130, 455/570, 455/63, 381/7
• US Class Current: 700/94
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A clock synthesis system may include a feed forward divider circuit configured to divide a source clock signal by one of a plurality of integers in response to a select signal to generate a reference clock that is synchronous to a synchronous pulse; a modulator that modulates the select signal in response to at least a difference value; a multiplier circuit that frequency multiplies the reference clock to generate an output clock; and a timing circuit that generates the difference value in response to the source clock and synchronous pulse.

Claims

1. A clock synthesis system, comprising:

a feed forward stage including a divider circuit configured to divide a source clock signal by one of a plurality of integers in response to a select signal to generate a reference clock that is synchronous to a synchronization pulse;

a modulator that modulates the select signal in response to at least a difference value;

a multiplier circuit that frequency multiplies the reference clock to generate an output clock, wherein the frequency multiplication of the reference clock is performed by a phase lock loop (PLL) circuit after the division of the source clock signal and the modulation of the select signal; and

a timing circuit that generates the difference value in response to the source clock signal and synchronization pulse.

2. The clock synthesis system of claim 1, wherein:

the modulator comprises a pulse density modulator; and

the divider circuit comprises a dual modulus prescaler that divides by integers L or L+1 in response to a logic state of the select signal.

3. The clock synthesis system of claim 1, wherein:

the modulator comprises a delta-sigma modulator that encodes at least the difference value into a pulse stream to generate the select signal.

4. The clock synthesis system of claim 1, wherein:

the timing circuit comprises a counter that generates the difference value by comparing an ideal count to a measured count of source clock cycles occurring between synchronous pulses.

5. The clock synthesis system of claim 1, wherein:

the multiplier circuit comprises a phase locked loop having a frequency dividing value Q and frequency multiplying value P, such that

f_output =P/Q * f_reference

where, f_output is the frequency of the output clock, f_reference is the frequency of the reference clock, and P and Q are integer values selected from a plurality of integer values.

6. The clock synthesis system of claim 1, further including:

serial communications interface configured to receive serial data synchronized with the synchronous pulse.

7. The clock synthesis system of claim 6, further including:

the serial communications interface is selected from;

a Universal Serial Bus (USB) interface or a S/PDIF interface.

8. A clock synthesis system, comprising:

a frequency synthesis circuit that divides a source clock by different integer values in response to at least a difference between the source clock and a synchronous clock to generate a reference clock, wherein the reference clock is an audio clock capable of being used to process audio data; and

a multiplier circuit that generates at least one output clock by frequency multiplying the reference clock, wherein the frequency multiplying of the reference clock is performed by a phase lock loop (PLL) circuit after the division of the source clock; and

wherein

the synchronous clock is slower than the source clock and the reference clock, and the at least one output clock is a rational multiple of, and synchronous with, the synchronous clock.

9. The clock synthesis system of claim 8, wherein:

the frequency synthesis circuit comprises a dual modulus prescaler circuit that divides the source clock by either integer L or L+1.

10. The clock synthesis system of claim 8, further including:

the multiplier circuit comprises a phase locked loop (PLL) having a frequency dividing value Q and frequency multiplying value P, where Q and P are integers; and

PLL configuration registers configured to receive values Q and Pas write values received from a source external to the clock synthesis system.

11. The clock synthesis system of claim 8, wherein:

the synchronous clock is generated from a synchronous event source selected from the group of;

a start-of-frame pulse for a serial communications signal, an alternate current (AC) line voltage, and a crystal oscillator output having a frequency less than 50 kHz.

12. The clock synthesis system of claim 8, wherein:

at least the frequency synthesis circuit comprises programmable logic circuits configured by configuration data.

13. The clock synthesis system of claim 8, further including:

a serial communications interface that generates the synchronous clock in response to signals on a serial communications channel; and

at least one data processing circuit that processes data transmitted in synchronism with the synchronous clock;

wherein

he at least one data processing circuit is selected from the group of;

data converter circuits that convert data in synchronism with the synchronous clock, including analog-to-digital converter circuits and digital-to-analog converter circuits;

encoding or decoding circuits that encode or decode data in synchronism with the synchronous clock; and

modulating or demodulating circuits that modulate at least one carrier signal with data or demodulate data from at least one modulated carrier signal.

14. The frequency synthesis system of claim 13, wherein:

the serial communications interface is selected from the group that includes;

a Universal Serial Bus Interface and a S/PDIF compatible interface.

15. A method, comprising:

dividing a source clock by multiple integer values based on a select signal to generate a reference clock signal that is synchronous with, and a rational multiple of, a synchronization pulse input;

modulating the select signal in response to at least a difference value generated in response to a difference between the synchronization pulse input and the source clock; and

frequency multiplying and filtering the reference clock signal to generate an output signal, wherein the frequency multiplying and filtering of the reference clock signal is performed by a phase lock loop (PLL) circuit after the dividing of the source clock and the modulating of the select signal.

16. The method of claim 15, wherein:

dividing the source clock includes dividing by an integer L or L+1 according to the select signal.

17. The method of claim 15, wherein:

modulating the select signal includes encoding at least a difference between an ideal value and the difference value into a variable pulse density signal.

18. The method of claim 15, further including:

receiving the synchronous pulse input at an external serial communication connection; and

processing data received at the serial connection in synchronism with the master clock.

19. The method of claim 18, wherein:

the synchronous pulse is generated in response to a Universal Serial Bus start-of-frame pulse.

20. The method of claim 18, wherein:

processing data includes steps selected from the group that includes;

generating analog output audio data in response to digital input audio data;

generating audio output data according to the FS standard; and

generating audio output data according to the S/PDIF standard.