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Clock synthesis systems, circuits and methods

  • US 9,002,488 B2
  • Filed: 12/29/2010
  • Issued: 04/07/2015
  • Est. Priority Date: 02/22/2010
  • Status: Active Grant
First Claim
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1. A clock synthesis system, comprising:

  • a feed forward stage including a divider circuit configured to divide a source clock signal by one of a plurality of integers in response to a select signal to generate a reference clock that is synchronous to a synchronization pulse;

    a modulator that modulates the select signal in response to at least a difference value;

    a multiplier circuit that frequency multiplies the reference clock to generate an output clock, wherein the frequency multiplication of the reference clock is performed by a phase lock loop (PLL) circuit after the division of the source clock signal and the modulation of the select signal; and

    a timing circuit that generates the difference value in response to the source clock signal and synchronization pulse.

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