Methods and systems for inspection of wafers and reticles using designer intent data

• US 9,002,497 B2
• Filed: 07/01/2004
• Issued: 04/07/2015
• Est. Priority Date: 07/03/2003
• Status: Active Grant

• Current Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Original Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Inventors: Volk, William, Wiley, James, Watson, Sterling, Kekare, Sagar A., Hess, Carl, Marella, Paul Frank, McCauley, Sharon, Chang, Ellis
• Primary Examiner(s): Bahta, Kidest
• Application Number:
  US10/883,372
• Publication Number:
  US 20050004774A1
• Time in Patent Office: 3,932 Days
• Field of Search: 700/121, 700/182, 700/98, 382/144, 382/149, 382/145, 382/202, 703/45, 703/14, 438/14, 356/237.23
• US Class Current: 700/121
• CPC Class Codes: G01N 2021/95676 Masks, reticles, shadow masks
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G03F 1/84 Inspecting
• CPC Class Codes: G03F 7/7065 Defects, e.g. optical inspection of patterned layer for defects
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0006 using a design-rule based approach
• CPC Class Codes: G06T 7/0008 checking presence/absence

Abstract

Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.

Claims

1. A computer-implemented method, comprising identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, wherein said identifying is performed using a computer processor, and wherein the reticle is used to form a pattern on the wafer prior to inspection of the wafer.

2. The method of claim 1, wherein the nuisance defects are formed on the wafer as a result of defects on the reticle that were determined to be permissible reticle defects.

3. The method of claim 1, wherein the nuisance defects are formed on the wafer as a result of defects on the reticle that were determined to he permissible reticle defects based on designer intent data.

4. The method of claim 1, further comprising separating the nuisance defects from actual defects on the wafer and processing data representative of the actual defects.

5. The method of claim 1, further comprising transmitting the inspection data from an inspection system used to perform the inspection of the reticle to the processor configured to perform the method.

6. The method of claim 1, further comprising transmitting the inspection data from a fab database to the processor configured to perform the method.

7. The method of claim 6, wherein said transmitting comprises sending coordinates of defects detected on the reticle and images of the defects.

8. The method of claim 1, wherein the inspection data comprises coordinates of a location of a defect on the reticle, the method further comprising translating the coordinates to coordinates of locations of one or more of the nuisance defects on the wafer.

9. The method of claim 1, further comprising determining if the nuisance detects will affect yield of semiconductor devices, wherein the semiconductor devices will be formed on the wafer.

10. The method of claim 1, wherein the nuisance defects are formed on the wafer as a result of defects on the reticle that were determined to be permissible reticle defects, the method further comprising analyzing the nuisance defects to determine if the permissible reticle defects were correctly classified.

11. The method of claim 10, wherein if the permissible reticle defects were not correctly classified, the method further comprising determining if the reticle should be analyzed, reworked, or disposed.

12. The method of claim 1, further comprising generating a two-dimensional map of the wafer, wherein the nuisance defects are distinguished from other defects in the map by one or more different designations.

13. A computer-implemented method, comprising identifying locations on a wafer in which nuisance defects will be formed based on inspection data produced by inspection of a reticle, wherein said identiing is performed using a computer processor.

14. The method of claim 13, further comprising selecting one or more parameters for wafer inspection such that the locations are not inspected.

15. The method of claim 13, further comprising selecting one or more parameters for wafer defect review such that the nuisance defects are not reviewed.

16. The method of claim 13, further comprising selecting one or more parameters for wafer defect analysis such that the nuisance defects are not analyzed.

17. A computer-implemented method, comprising:

identifying critical portions of a wafer based on criticality associated with different areas of the wafer; and

selecting parameters for inspection of the wafer such that only the critical portions of the wafer are inspected, wherein said identifying and said selecting are performed using a computer processor.

18. The method of claim 17, wherein the parameters are selected such that the critical portions having different criticalities are inspected with different parameters.

19. The method of claim 17, further comprising translating coordinates of a location of a detect detected on a reticle to coordinates of locations of one or more detects on the wafer and analyzing the printability of the detect detected on the reticle.

20. The method of claim 17, further comprising translating coordinates of a location. of a defect detected on a reticle to coordinates of locations of one or more defects on the wafer and removing inspection data at the coordinates on the wafer from wafer inspection data.

21. The method of claim 17, further comprising generating one or more two-dimensional maps illustrating the critical portions of the wafer.

22. The method of claim 17, wherein said selecting comprises selecting the parameters such that nuisance defects on the wafer are not classified as actual defects.

23. The method of claim 17, further comprising assigning a designation to a defect on the wafer based on the criticality of the critical portion in which the defect is located.

24. The method of claim 17, further comprising determining processing of a defect on the wafer based on the criticality of the critical portion in which the defect is located.

25. The method of claim 17, further comprising setting one or more parameters for classification of defects on the wafer based on the criticality of the critical portions.

26. The method of claim 17, further comprising classifying defects on the wafer as critical defects or non-critical defects and analyzing a process performed on the wafer based on the critical defects and the non-critical defects.

27. The method of claim 17, further comprising classifying defects on the wafer as critical defects or non-critical defects and processing the critical defects separately from the non-critical defects.

28. The method of claim 17, further comprising discarding inspection data representing defects in one of the critical portions if the defects have a lateral dimension smaller than a predetermined threshold and if other features in the one portion have a lateral dimension greater than the predetermined threshold.

29. The method of claim 17, further comprising discarding inspection data representing defects in one of the critical portions if an element of a circuit in the one portion has a predetermined amount of redundancy and if defects in the one portion do not exceed a predetermined density threshold.

30. The method of claim 17, wherein the inspection is performed on one level of the wafer, the method further comprising identifying the criticality of a defect on the wafer based on the criticality of the critical portion in which the defect is located and data representative of at least one layer of the water above or below the one level.

31. The method of claim 30, further comprising generating a three-dimensional representation of the defect, the one level, and the at least one layer of the wafer.

32. A computer-implemented method, comprising determining one or more parameters for wafer defect review based on criticality associated with different areas of the water, wherein said determining is performed using a computer processor.

33. The method of claim 32, further comprising selecting the one or more parameters such that only defects located in critical portions of the wafer are reviewed.

34. The method of claim 33, wherein the one or more parameters are different for one or more of the critical portions.

35. The method of claim 32, further comprising sending information about the criticality to a tool configured to perform the wafer defect review.

36. A computer-implemented method, comprising determining one or more parameters for wafer defect analysis based on criticality associated with different areas of the wafer, wherein said determining is performed using a computer processor.

37. The method of claim 36, further comprising selecting the one or more parameters such that only defects located in critical portions of the wafer are analyzed.

38. The method of claim 37, wherein the one or more parameters are different for one or more of the critical portions.

39. The method of claim 36, further comprising sending information about the criticality to a tool configured to perform the wafer defect analysis.