Method, apparatus and instructions for parallel data conversions

• US 9,002,914 B2
• Filed: 03/15/2013
• Issued: 04/07/2015
• Est. Priority Date: 09/08/2003
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ramanujam, Gopalan
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US13/843,339
• Publication Number:
  US 20130218936A1
• Time in Patent Office: 753 Days
• Field of Search: 708/204
• US Class Current: 708/204
• CPC Class Codes: G06F 15/82 data or demand driven
• CPC Class Codes: G06F 7/48 using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/384 Register renaming

Abstract

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits. The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Claims

1. A processor comprising:

a first register;

a decoder to decode an instruction;

a functional unit coupled with the decoder and the first register to convert, responsive to the instruction being decoded, a first packed first format value in a first format selected from a first plurality of packed first format values in the first format to a first plurality of second format values, said first packed first format value having a plurality of sub elements each having a first number of bits, each of the first plurality of second format values being a number represented in a second format and having a second number of bits which is greater than the first number of bits, said functional unit to store all of said first plurality of second format values into said first register.

2. The processor of claim 1 wherein the second number of bits is a power-of-two multiple of the first number of bits, and wherein the first plurality of second format values comprises at least four second format values.

3. The processor of claim 2 wherein a source specifier is to specify either a second register or a memory location as a source storage location and further wherein a destination specifier is to specify the first register as a destination storage location.

4. The processor of claim 3 wherein said first format is an integer format and wherein said second format is a floating point format.

5. The processor of claim 3 wherein said first register and said second register are part of a first group of architectural registers, the first group of architectural registers having a first size.

6. The processor of claim 1 wherein said functional unit chooses one of said first plurality of packed first format values to convert based on an immediate operand value.

7. The processor of claim 1 wherein an opcode portion of said instruction specifies which of said first plurality of packed first format values to convert.

8. The processor of claim 1 further comprising a register renaming circuit, wherein the first register has a correspondence to an architectural register, said correspondence being tracked by the register renaming circuit.

9. The processor of claim 1 wherein said instruction comprises an opcode and an operand specifier, wherein the operand specifier is in a MOD R/M format.

10. The processor of claim 8 wherein said first plurality of packed first format values are N bit integer values and wherein said first packed first format value is an N bit integer value, wherein said plurality of sub elements is M sub elements and wherein each of the M sub elements has N/M bits, and further wherein each of the first plurality of second format values is an N-bit floating point result.

11. The processor of claim 1 further comprising a second register, wherein said functional unit is further responsive to a second instruction being decoded to convert a second plurality of second format values in the second format having the second number of bits to a second first format value and to store the second first format value in one of a plurality of packed first format value positions in said second register, wherein said second first format value comprises saturated representations of the second plurality of second format values in the first format.

12. A processor comprising:

a decoder to receive a first instruction and to decode said first instruction;

a functional unit coupled to the decoder, the functional unit in response to the first instruction being decoded to convert a first plurality of floating point values in a first floating point format having a first number of bits into a first integer value comprising a plurality of sub elements each having a second number of bits less than the first number of bits and to store said first integer value in a first position in a first register, the first register being capable of storing a plurality of integer values in a plurality of individually accessible positions.

13. The processor of claim 12 wherein said first instruction comprises an opcode, a first operand specifier, an immediate operand, and a second operand specifier, wherein the first operand specifier is to specify a source from which the functional unit is to retrieve the first plurality of floating point numbers, the second operand specifier is to specify the first register from a plurality of registers, and wherein the immediate operand is to specify one of a plurality of locations in the first register in which the first integer value is to be stored.

14. The processor of claim 13 wherein said decoder is to decode a second instruction, and wherein said functional unit, responsive to the second instruction being decoded, is to convert a second integer value to a second plurality of floating point values in the first floating point format and to store said second plurality of floating point values into a second register.

15. The processor of claim 14 wherein said first register and said second register are part of a first group of architectural registers, and further wherein said plurality of sub elements comprise saturated representations of said first plurality of floating point values.

16. The processor of claim 13, wherein the first integer value has at least four sub elements.

17. A machine readable medium, which is one of a memory and a storage, and which stores an instruction, which if executed by a machine, causes the machine to perform operations comprising:

converting an integer value, the integer value being among a plurality of integer values of a packed data and having a first integer format having a plurality of sub elements each having a first number of bits, to a plurality of floating point values, each of the plurality of floating point values having a first floating point format, the first floating point format having a multiple of the first number of bits;

storing the plurality of floating point values into a first register.

18. The machine readable medium of claim 17, wherein said machine readable medium further stores a second instruction, which if executed by the machine, cause the machine to perform operations comprising:

converting a second plurality of floating point values in the first floating point format to a second integer value in the first integer format;

storing the second integer value in a second register.

19. A processor comprising:

a first register;

a decoder to decode an instruction; and

a functional unit coupled with the decoder and the first register to convert, responsive to one or more control signals decoded from the instruction, an integer value of a plurality of integer values of a packed data that is to have a first integer format that is to have a plurality of sub elements that are each to have a first number of bits, to a plurality of floating point values, each of the plurality of floating point values to have a first floating point format, the first floating point format to have a multiple of the first number of bits, the functional unit to store the plurality of the floating point values in the first register.

20. The processor of claim 19, wherein the integer value is to have at least four sub elements.

21. The processor of claim 19, wherein said functional unit is to choose the integer value based on an immediate operand value.