Methods, systems, and articles of manufacture for implementing a physical electronic design with area-bounded tracks

• US 9,003,349 B1
• Filed: 06/28/2013
• Issued: 04/07/2015
• Est. Priority Date: 06/28/2013
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Salowe, Jeffrey
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US13/931,503
• Time in Patent Office: 648 Days
• Field of Search: 716/129, 716/130, 716/131, 716/122, 716/123, 703/15
• US Class Current: 716/129
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed are methods, systems, and articles of manufacture for implementing a physical electronic design with area-bounded tracks. One aspect identifies an area in an electronic design and a track pattern associated with the area, identifies active tracks in the track pattern, and creates spacetiles with the active tracks. This aspect uses area-based search probes based on spacetiles to find viable implementation solutions to implement the area in the electronic design. Another aspect identifies a tracked area associated with a track pattern and a trackless area and use spacetile(s) and a via spacetile layer to transition between the tracked area and the trackless area for implementation of the electronic design in the tracked or the trackless area of the electronic design.

Claims

1. A computer implemented method for implementing a physical electronic design with area-bounded tracks, comprising:

executing a sequence of instructions with at least one processor or at least one processor core of a computing system to perform a process, the process comprising;

identifying a region and a first region operatively coupled to the region in an area of an electronic design;

identifying a track pattern for the region and a first track pattern for the first region, wherein the track pattern includes multiple tracks used for implementing the region of the electronic design, and the track pattern and the first track pattern have different combinations of widths or spacing values associated with respective tracks; and

implementing the region and the first region of the electronic design by using at least an area probe derived from a track in the track pattern.

2. The computer implemented method of claim 1, the process further comprising:

determining whether or not the region is tracked; and

performing a spacetile punch on the track in the track pattern to create a spacetile, wherein the spacetile is used for the area probe.

3. The computer implemented method of claim 2, the process further comprising:

determining whether the track is active; and

using the area probe to search for viable solutions for implementing the region of the electronic design.

4. The computer implemented method of claim 1, the process further comprising:

determining whether an on-track requirement is a hard requirement, a soft requirement, or a don'"'"'t-care requirement for the region;

determining a penalty for violation of the on-track requirement, where the on-track requirement is determined to be a soft requirement; and

permitting free-form implementation in the region of the electronic design, where the on-track requirement is determined to be a don'"'"'t-care requirement.

5. The computer implemented method of claim 1, the process further comprising:

identifying all active tracks in the track pattern associated with the region;

performing a spacetile punch process on the all active tracks in the track pattern to form multiple spacetiles prior to implementing the region of the electronic design; and

determining the area probe by using the multiple spacetiles.

6. The computer implemented method of claim 1, the process further comprising:

identifying all active tracks in the track pattern associated with the region;

updating the area probe during implementation of the region of the electronic design by performing a spacetile punch process on a number of active tracks fewer than a total number of the all active tracks; and

implementing the region of the electronic design by using the area probe that is updated during and prior to completion of implementation of the region of the electronic design.

7. The computer implemented method of claim 1, the process further comprising:

identifying a boundary for the region;

determining intersections between the track and the boundary of the region; and

determining a track segment for the track in the track pattern based at least in part upon on the intersections.

8. The computer implemented method of claim 1, the process further comprising:

identifying an existing circuit feature in the region; and

determining an additional spacetile by performing a spacetile punch process on the existing circuit feature.

9. A system for implementing a physical electronic design with area-bounded tracks, comprising:

non-transitory computer readable storage medium storing thereupon program code that includes a sequence of instructions;

at least one processor or at least one processor core executing the sequence of instructions of the program code to;

identify a region and a first region operatively coupled to the region in an area of an electronic design;

identify a track pattern for the region and a first track pattern for the first region, wherein the track pattern includes multiple tracks used for implemented the region of the electronic design, and the track pattern and the first track pattern have different combinations of widths or spacing values associated with respective tracks; and

implement the region and the first region of the electronic design by using at least an area probe derived from a track in the track pattern.

10. The system of claim 9, in which the at least one processor or the at least one processor core is further to:

execute one or more sets of instructions of multiple sets of instructions to implement the physical electronic design with the area-bounded tracks, wherein;

a first set of instructions of the multiple sets of instructions comprises a first sequence of instructions which, when executed by the at least one processor, causes the at least one processor to;

determine whether or not the region is tracked; and

perform a spacetile punch on the track in the track pattern to create a spacetile, wherein the spacetile is used for the area probe;

a second set of instructions of the multiple sets of instructions comprises a first sequence of instructions which, when executed by the at least one processor, causes the at least one processor to;

determine whether an on-track requirement is a hard requirement, a soft requirement, or a don'"'"'t-care requirement for the region;

determine a penalty for violation of the on-track requirement, where the on-track requirement is determined to be a soft requirement; and

permit free-form implementation in the region of the electronic design, where the on-track requirement is determined to be a don'"'"'t-care requirement; and

a third set of instructions of the multiple sets of instructions comprises a first sequence of instructions which, when executed by the at least one processor, causes the at least one processor to;

identify all active tracks in the track pattern associated with the region;

perform a spacetile punch process on the all active tracks in the track pattern to form multiple spacetiles prior to implementing the region of the electronic design; and

determine the area probe by using the multiple spacetiles.

11. The system of claim 10, in which the at least one processor or the at least one processor core is further to:

determine whether the track is active; and

use the area probe to search for viable solutions for implementing the region of the electronic design.

12. The system of claim 9, in which the at least one processor or the at least one processor core is further to:

execute one or more sets of instructions of multiple sets of instructions to implement the physical electronic design with the area-bounded tracks, wherein

a first set of instructions of the multiple sets of instructions comprises a first sequence of instructions which, when executed by the at least one processor, causes the at least one processor to;

identify all active tracks in the track pattern associated with the region;

update the area probe during implementation of the region of the electronic design by performing a spacetile punch process on a number of active tracks fewer than a total number of the all active tracks; and

implement the region of the electronic design by using the area probe that is updated during and prior to completion of implementation of the region of the electronic design;

a second set of instructions of the multiple sets of instructions comprises a first sequence of instructions which, when executed by the at least one processor, causes the at least one processor to;

identify a boundary for the region;

determine intersections between the track and the boundary of the region; and

determine a track segment for the track in the track pattern based at least in part upon on the intersections; and

a third set of instructions of the multiple sets of instructions comprises a first sequence of instructions which, when executed by the at least one processor, causes the at least one processor to;

identify an existing circuit feature in the region; and

determine an additional spacetile by performing a spacetile punch process on the existing circuit feature.

13. The system of claim 9, in which the at least one processor or the at least one processor core is further to:

determine whether or not the region is tracked; and

perform a spacetile punch on the track in the track pattern to create a spacetile, wherein the spacetile is used for the area probe.

14. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a method for implementing a physical electronic design with area-bounded tracks, the method comprising:

identifying a region and a first region operatively coupled to the region in an area of an electronic design;

identifying a track pattern for the region and a first track pattern for the first region, wherein the track pattern includes multiple tracks used for implemented the region of the electronic design, and the track pattern and the first track pattern have different combinations of widths or spacing values associated with respective tracks; and

implementing the region and the first region of the electronic design by using at least an area probe derived from a track in the track pattern.

15. The article of manufacture of claim 14, the process further comprising:

determining whether or not the region is tracked; and

performing a spacetile punch on the track in the track pattern to create a spacetile, wherein the spacetile is used for the area probe.

16. The article of manufacture of claim 15, the process further comprising:

determining whether the track is active; and

using the area probe to search for viable solutions for implementing the region of the electronic design.

17. The article of manufacture of claim 15, the process further comprising:

determining whether an on-track requirement is a hard requirement, a soft requirement, or a don'"'"'t-care requirement for the region;

determining a penalty for violation of the on-track requirement, where the on-track requirement is determined to be a soft requirement; and

permitting free-form implementation in the region of the electronic design, where the on-track requirement is determined to be a don'"'"'t-care requirement.

18. The article of manufacture of claim 15, the process further comprising:

identifying all active tracks in the track pattern associated with the region;

performing a spacetile punch process on the all active tracks in the track pattern to form multiple spacetiles prior to implementing the region of the electronic design; and

determining the area probe by using the multiple spacetiles.

19. The article of manufacture of claim 15, the process further comprising:

identifying all active tracks in the track pattern associated with the region;

updating the area probe during implementation of the region of the electronic design by performing a spacetile punch process on a number of active tracks fewer than a total number of the all active tracks; and

implementing the region of the electronic design by using the area probe that is updated during and prior to completion of implementation of the region of the electronic design.

20. The article of manufacture of claim 15, the process further comprising:

performing one or more sub-processes of multiple sub-processes, wherein

a first sub-process of the multiple sub-processes comprises;

identifying a boundary for the region;

determining intersections between the track and the boundary of the region; and

determining a track segment for the track in the track pattern based at least in part upon on the intersections; and

a second sub-process of the multiple sub-processes comprises;

identifying an existing circuit feature in the region; and

determining an additional spacetile by performing a spacetile punch process on the existing circuit feature.

21. A computer implemented method for implementing a physical electronic design with area-bounded tracks, comprising executing a sequence of instructions with a processor or a processor core that executes one or more threads in a computing system to perform a process, the process comprising:

identifying a tracked region and a track pattern associated with the first region in an electronic design;

identifying a trackless region in the electronic design; and

implementing at least a part of the tracked region, a part of the trackless region, and transition between the track region and the trackless region.

22. The computer implemented method of claim 21, the process further comprising:

performing one or more sub-processes of multiple sub-processes, wherein

a first sub-process of the multiple sub-processes comprises;

identifying a requirement for the tracked region;

performing a spacetile punch on a track in the track pattern to create a first spacetile for the tracked region; and

implementing the tracked region of the electronic design by using an area probe;

a second sub-process of the multiple sub-process comprises;

identifying an existing circuit feature in the trackless region; and

performing a spacetile punch on the existing circuit feature to create a second spacetile for the trackless region; and

a third sub-process of the multiple sub-process comprises;

identifying or creating a via spacetile layer; and

aggregating existing circuit features in both the tracked region and the trackless region into the via spacetile layer, when the existing circuit features are determined to exist prior to implementation of the electronic design in the tracked region and the trackless region.

23. The computer implemented method of claim 22, the third sub-process further comprising:

determining or identifying a direction of transitioning between the tracked region and the trackless region;

selecting one or more spacetiles from either the tracked region or the trackless region based at least in part upon the direction of transitioning; and

aggregating the one or more spacetiles to the via spacetile layer.

24. The computer implemented method of claim 23, the third sub-process further comprising:

determining a resulting area probe based at least in part upon the one or more spacetiles that are aggregated to the via spacetile layer; and

implementing the electronic design by using at least the resulting area probe.

25. The computer implemented method of claim 21, wherein the tracked region and the trackless region are on a same layer or on two different layers of the electronic design.