Abstracting a multithreaded processor core to a single threaded processor core

• US 9,003,410 B2
• Filed: 01/30/2007
• Issued: 04/07/2015
• Est. Priority Date: 01/30/2007
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Norton, Scott J., Kim, Hyun
• Primary Examiner(s): SWIFT, CHARLES M
• Application Number:
  US11/700,748
• Publication Number:
  US 20080184233A1
• Time in Patent Office: 2,989 Days
• Field of Search: None
• US Class Current: 718/100
• CPC Class Codes: G06F 2209/5018 Thread allocation
• CPC Class Codes: G06F 2209/5021 Priority
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: G06F 9/48 Program initiating; Program switching, e.g. by interrupt
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/485 Task life-cycle, e.g. stopping, restarting, resuming execution G06F9/4881 takes precedence
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/50 Allocation of resources, e.g. of the central processing unit [CPU]
• CPC Class Codes: G06F 9/5005 to service a request
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/5044 considering hardware capabilities

Abstract

In an embodiment of the invention, an apparatus and method to abstract a multithreaded processor core to single threaded processor core include performing the steps of: viewing, by an operating system, a first hardware thread and a second hardware thread in a processor core; and viewing, by a user application, the first hardware thread and the second hardware thread as a single CPU object.

Claims

1. A system comprising non-transitory tangible computer-readable storage media encoded with operating-system code configured to, when executed by a multi-threaded multi-core processor:

recognize and schedule processes for execution on each of plural hardware threads of said processor; and

represent said processor to a client application as having multiple cores with a single hardware thread per core only while an attribute for said client application is not set, said operating-system code being further configured to, when said attribute is set, represent each of said hardware threads to said client application.

2. A system as recited in claim 1 further comprising said processor, each core of said processor having plural sibling hardware threads.

3. A method comprising:

recognizing and scheduling processes for execution on each of plural hardware threads of a processor; and

representing said processor to a client application as having multiple cores with a single hardware thread per core only while an attribute for said client application is not set, said operating-system code being further configured to, when said attribute is set, represent each of said hardware threads to said client application.

4. A method as recited in claim 3, wherein each core of said processor has plural sibling hardware threads.

5. An apparatus comprising:

a computer system including a processor and an operating system, wherein the operating system;

recognizes and schedules processes for execution on each of plural hardware threads of said processor; and

represents said processor to a client application as having multiple cores with a single hardware thread per core only while an attribute for said client application is not set, said operating-system code being further configured to, when said attribute is set, represent each of said hardware threads to said client application.

6. An apparatus as recited in claim 5, wherein each core of said processor has plural sibling hardware threads.