Radiation detectors and methods of fabricating radiation detectors

• US 9,006,010 B2
• Filed: 11/22/2011
• Issued: 04/14/2015
• Est. Priority Date: 11/22/2011
• Status: Active Grant

• Current Assignee: GE Medical Systems Israel, Ltd (GE Healthcare Technologies, Inc.)
• Original Assignee: General Electric Company
• Inventors: Shahar, Arie, Traub, Eliezer, Sclar, Diego, Rusian, Peter
• Primary Examiner(s): Monbleau, Davienne
• Assistant Examiner(s): Cruz, Leslie Pilar
• Application Number:
  US13/302,835
• Publication Number:
  US 20130126998A1
• Time in Patent Office: 1,239 Days
• Field of Search: 438/57, 438/439, 438/959, 438/693, 438/40, 438/701, 438/713, 438/735, 438/738, 438/739, 257/428, 257/431, 257/623, 257/E21.237, 257/E21.214, 257/E21.219, 257/E21.223, 257/E21.309
• US Class Current: 438/40
• CPC Class Codes: H01L 31/085 the device being sensitive to very short wavelength, e.g. X-ray, Gamma-rays
• CPC Class Codes: H01L 31/115 Devices sensitive to very short wavelength, e.g. X-rays, gamma-rays or corpuscular radiation
• CPC Class Codes: H01L 31/18 Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• CPC Class Codes: Y10S 438/959 Mechanical polishing of wafer

Abstract

Radiation detectors and methods of fabricating radiation detectors are provided. One method includes mechanically polishing at least a first surface of a semiconductor wafer using a polishing sequence including a plurality of polishing steps, wherein a last polishing step of the polishing sequence includes polishing with a slurry having a grain size smaller than about 0.1 μm to create a polished first surface. The method also includes applying (i) an encapsulation layer on a top of the polished first surface to seal the polished first surface and (ii) a photoresist layer on top of the encapsulation layer on the polished first surface. The method further includes creating undercuts of the encapsulation layer under the photoresist layer. The method additionally includes partially etching the polished first surface of the semiconductor via the openings in the photoresist layer and in the encapsulation layer to partially etch the semiconductor creating etched regions.

Claims

1. A method for fabricating a radiation detector, the method comprising:

mechanically polishing at least a first surface of a semiconductor wafer using a polishing sequence including a plurality of polishing steps, wherein a last polishing step of the polishing sequence includes polishing with a slurry having a grain size smaller than about 0.1 μ

m to create a polished first surface;

applying (i) an encapsulation layer on a top of the polished first surface to seal the polished first surface and (ii) a photoresist layer on top of the encapsulation layer on the polished first surface;

creating openings in the photoresist layer;

partially etching the encapsulation layer via the openings in the photoresist layer to partially remove the encapsulation layer and creating undercuts of the encapsulation layer under the photoresist layer;

partially etching the polished first surface of the semiconductor wafer via the openings in the photoresist layer and in the encapsulation layer to partially etch the semiconductor wafer creating etched regions, in the first surface, having undercuts of the semiconductor wafer under the encapsulation layer to produce non-etched gap regions between the etched regions of the polished first surface;

etching a second surface of the semiconductor wafer;

applying pixelated anode electrodes in the etched regions of the polished first surface and a monolithic cathode electrode on a second surface of the semiconductor wafer; and

removing the photoresist layer by a liftoff process.

2. The method of claim 1, wherein the polishing forms the polished first surface having a resistivity substantially the same as a bulk resistivity of the semiconductor wafer.

3. The method of claim 1, wherein applying the photoresist layer comprises using photolithography.

4. The method of claim 1, wherein the partial etching forms the gap regions having a resistivity substantially the same as a bulk resistivity of the semiconductor wafer.

5. The method of claim 1, wherein the partial etching produces in the etched regions a semiconductor rich with a semiconductor component.

6. The method of claim 1, wherein the etching of the second surface produces in the etched regions a semiconductor rich with a semiconductor component.

7. The method of claim 1, wherein the semiconductor wafer comprises Cadmium Zinc Telluride.

8. The method of claim 7, wherein the encapsulation layer comprises Zinc Sulfide.

9. The method of claim 1, wherein the pixelated anode electrodes and the cathode electrode are formed from a metal, the metal being at least one of Indium, Gold, Platinum or Aluminum.

10. The method of claim 1, wherein the pixelated anode electrodes and the cathode electrode are applied to the semiconductor wafer by a processing technique including one of evaporation, spattering, electroplating or electro-less plating.

11. The method of claim 1, wherein the pixelated anode electrodes and the cathode electrode produced with said semiconductor wafer are formed from electrical contacts being one of Ohmic contacts or blocking contacts.

12. The method of claim 1, wherein the first and second surfaces of the semiconductor wafer are polished simultaneously in a same fabrication step.

13. The method of claim 1, wherein the first and second surfaces of the semiconductor wafer are polished in a plurality of different fabrication steps.

14. The method of claim 1, wherein the first and second surfaces of the semiconductor wafer are etched simultaneously in a same fabrication step.

15. The method of claim 1, wherein the first and second surfaces of the semiconductor wafer are etched in a plurality of different fabrication steps.

16. The method of claim 1, wherein the pixelated anode electrodes and the cathode electrode are applied to the semiconductor wafer simultaneously in a same fabrication step.

17. The method of claim 1, wherein the pixelated anode electrodes and the cathode electrode are applied to the semiconductor wafer in a plurality of different fabrication steps.

18. The method of claim 1, wherein (i) partially etching the polished first surface of the semiconductor wafer via the openings in the photoresist layer and in the encapsulation layer and (ii) etching the second surface of the semiconductor wafer are performed simultaneously is one step.

19. The method of claim 1, wherein the photoresist comprises one of a positive photoresist and a negative photoresist.

20. The method claim of claim 1, wherein the last polishing step includes a slurry having grain size of about 0.05 μ

m.