Fabrication of three-dimensional high surface area electrodes

• US 9,006,014 B2
• Filed: 12/13/2013
• Issued: 04/14/2015
• Est. Priority Date: 12/13/2012
• Status: Active Grant

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Mujeeb-U-Rahman, Muhammad, Scherer, Axel
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US14/106,701
• Publication Number:
  US 20140167257A1
• Time in Patent Office: 487 Days
• Field of Search: 438/49, 438/668, 438/702, 438/FOR.363
• US Class Current: 438/49
• CPC Class Codes: A61B 2562/125 characterised by the manufacture of electrodes
• CPC Class Codes: B81B 2201/0214 Biosensors; Chemical sensors
• CPC Class Codes: B81B 2203/04 Electrodes
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81C 1/00111 Tips, pillars, i.e. raised structures microneedles A61M37/0015
• CPC Class Codes: B81C 1/0038 Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373
• CPC Class Codes: B81C 2203/0714 Forming the micromechanical structure with a CMOS process
• CPC Class Codes: H01L 21/02425 Conductive materials, e.g. metallic silicides
• CPC Class Codes: H01L 21/285 from a gas or vapour, e.g. condensation
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 2224/1401 Structure
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 2924/11 Device type
• CPC Class Codes: H01L 31/00 Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof H10K30/00 takes precedence; devices consisting of a plurality of solid state components formed in, or on, a common substrate, other than combinations of radiation-sensitive components with one or more electric light sources, H01L27/00
• CPC Class Codes: H01L 33/387 with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer

Abstract

A method for fabricating three dimensional high surface electrodes is described. The methods including the steps: designing the pillars; selecting a material for the formation of the pillars; patterning the material; transferring the pattern to form the pillars; insulating the pillars and providing a metal layer for increased conductivity. Alternative methods for fabrication of the electrodes and fabrication of the electrodes using CMOS are also described.

Claims

1. A method for fabricating three dimensional high surface electrodes, comprising:

designing a plurality of pillars by optimizing one or more characteristics of the pillars, wherein the plurality of pillars corresponds to one or more electrodes dependent on an isolation provided to the plurality of pillars;

applying a resist onto a substrate, wherein the substrate is silicon or silicon alloy;

patterning the resist, wherein the patterning defines the plurality of pillars to be formed on the substrate;

removing selected portions of the substrate via etching corresponding to the pattern of the resist to form the plurality of pillars, the etching forming a pillar with an aspect ratio greater than 5;

insulating a first group of pillars of the plurality of pillars from other pillars of the plurality of pillars to form one distinct electrode by forming an insulator layer with complete and uniform coverage over the first group of pillars of the plurality of pillars; and

depositing a 10 nm to 500 nm metal layer on the plurality of pillars to increase the conductivity of a surface of the electrode, wherein the metal layer coverage is complete and uniform over the plurality of pillars.

2. The method according to claim 1, wherein the thickness of the insulator layer is between 50 nm and 250 nm.

4. The method according to claim 1, wherein the thickness of the metal layer is between 50 nm and 250 nm.

5. The method according to claim 1, wherein the pillars have an aspect ratio between 15 and 20.

6. The method for fabricating three dimensional high surface electrodes according to claim 1, further comprising:

depositing a plurality of particles on top of the metal layer of the plurality of pillars to increase the surface area of the pillars,

wherein

the particles are deposited via spray or spin techniques, and

the particles are selected corresponding to a size of a species to be detected by the electrode.

7. The method according to claim 6, wherein the particles are either nanoparticles or microparticles.

8. The method according to claim 1, wherein the depositing of the metal layer on the plurality of pillars is performed using pressure and a stage adapted to be rotated and tilted with respect to the metal being deposited.

9. The method according to claim 8, wherein the pressure used during metal deposition is 20 mTorr.

10. The method according to claim 1, wherein the temperature is below 250°

C.

3. A method for fabricating three dimensional high surface electrodes from CMOS on a metal that is not silicon, comprising:

designing a plurality of pillars by optimizing one or more characteristics of the pillars, wherein the plurality of pillars corresponds to one or more electrodes dependent on an isolation provided to the plurality of pillars;

selecting a top most metal layer from the CMOS where the pillars will be formed, wherein the top most metal layer is not silicon;

applying a resist onto the top most metal layer of the CMOS;

patterning the resist, wherein the patterning defines where the plurality of pillars will be formed on the top most metal layer of the CMOS;

removing selected portions of the top most metal layer of the CMOS via etching corresponding to the pattern of the resist to form the plurality of pillars, the etching forming a pillar with an aspect ratio greater than 5; and

depositing a 10 nm to 500 nm metal layer on the plurality of pillars to increase conductivity of a surface of the electrode, wherein a coverage of the metal layer coverage is complete and uniform over the plurality of pillars,

wherein the method for fabricating is performed at temperatures below 500°

C.

11. The method according to claim 3, wherein the thickness of the metal layer is between 50 nm and 250 nm.

12. The method according to claim 3, wherein the pillars have an aspect ratio between 15 and 20.

13. The method for fabricating three dimensional high surface electrodes according to claim 3, further comprising:

depositing a plurality of particles on top of the metal layer of the plurality of pillars to increase the surface area of the pillars,

wherein

the particles are deposited via spray or spin techniques, and

the particles are selected corresponding to a size of a species to be detected by the electrode.

14. The method according to claim 3, wherein the depositing of the metal layer on the plurality of pillars is performed using pressure and a stage adapted to be rotated and tilted with respect to the metal being deposited.

15. The method according to claim 3, wherein the temperature is below 250°

C.