Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching

• US 9,006,053 B2
• Filed: 04/29/2014
• Issued: 04/14/2015
• Est. Priority Date: 02/11/2005
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Original Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Inventors: Pan, Ji, Ng, Daniel, Tai, Sung-Shan, Bhalla, Anup
• Primary Examiner(s): PHAM, THANHHA S
• Application Number:
  US14/264,318
• Publication Number:
  US 20140235024A1
• Time in Patent Office: 350 Days
• Field of Search: 438/142, 438/167, 438/259, 438/270, 438/534, 257/E21.655
• US Class Current: 438/167
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/82 to produce devices, e.g. integrated circuits, each consisting of a plurality of components
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<TBCD is created into side walls of TCT and beneath SCD. An embedded Shannon implant region (ESIR) is created into sub-contact trench zone (SCTZ) beneath TCT floor. A metal layer is formed in contact with ESIR, body and source region. The metal layer also fills TCT and covers dielectric region thus completing the MOSFET/SKY with only one-time etching of its TCT.

Claims

1. A method for fabricating a MOSFET integrated with Schottky diode (MOSFET/SKY), expressed in an X-Y-Z Cartesian coordinate system with the X-Y plane parallel to its major semiconductor chip plane, comprising:

a) forming, in an epitaxial layer overlaying a semiconductor substrate, a gate trench and depositing gate material therein;

b) forming a body region in the epitaxial layer, a source region atop the body region and a dielectric region atop the gate trench and the source region;

c) etching a top contact trench (TCT) with vertical side walls defining a X-Y cross sectional boundary for containing a Schottky diode there within, said X-Y cross sectional boundary

c1) going through the dielectric region and the source region thus defining a source-contact depth (SCD); and

c2) going partially into the body region by a predetermined total body-contact depth (TBCD);

d) creating;

d1) into the side walls of the TCT and beneath the SCD, a heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<

TBCD; and

d2) into a sub-contact trench zone (SCTZ) beneath the floor of the TCT, an embedded Shannon implant region (ESIR); and

e) forming a metal layer;

e1) in contact with the ESIR, the body region and the source region; and

e2) filling the TCT and covering the dielectric region whereby completing the MOSFET/SKY with only one-time etching of its TCT.

2. The method of claim 1 wherein creating the heavily-doped EBIR and the ESIR comprising:

d11) implanting the heavily-doped EBIR while keeping the SCTZ essentially free of any concomitant body-contact implantation; and

d21) implanting the ESIR into the SCTZ.

3. The method of claim 2 wherein implanting the heavily-doped EBIR while keeping the SCTZ essentially free of any concomitant body-contact implantation comprising:

d111) forming a lower spacer sub-layer (LSSL) of horizontal wall thickness (HWT_LS) atop the side walls of the TCT and of vertical wall thickness (VWT_LS) atop the bottom floor of the TCT and atop the dielectric region with VWT_LS essentially equal to HWT_LS;

d112) atop the LSSL, forming an upper spacer sub-layer (USSL) of horizontal wall thickness (HWT_US) atop the side walls of the TCT, of lower vertical wall thickness (LVWT_US) atop the bottom floor of the TCT and of upper vertical wall thickness (UVWT_US) atop the dielectric region with UVWT_US essentially equal to HWT_US but LVWT_US>

>

HWT_US;

d113) selecting the LSSL material and the USSL material such that;

the LSSL would allow a through-transmission of a later body-implant beam while the USSL would, with a sufficiently large layer thickness, block a through-transmission of the later body-implant beam; and

the LSSL acts as an etch-stop for a later USSL-etching step;

d114) implanting, with the body-implant beam at a planetary body-implant tilt angle (BITA) with respect to the Z-axis and through a combined wall thickness of HWT_US+HWT_LS, the heavily-doped EBIR while, owing to the relationship LVWT_US>

>

HWT_US, keeping the SCTZ essentially free of any concomitant body-contact implantation whereby avoiding the otherwise concomitant body-contact implantation, into the SCTZ and bridging the EBIR, that would require an undesirable additional etching of the TCT to remove; and

d115) successively removing the USSL and the LSSL with an USSL-etching step and a LSSL-etching step.

4. The method of claim 3 wherein LVWT_US>

3*HWT_US.

5. The method of claim 3 wherein:

the LSSL material is silicon nitride and the USSL material is high density plasma deposited silicon oxide (HDPSO);

VWT_LS is from 100 to 500 Angstrom;

UVWT_US is less than 0.1 micron while LVWT_US is from 0.3 to 0.4 micron; and

The planetary BITA is from 15 to 30 degrees.

6. The method of claim 2 wherein implanting the ESIR into the SCTZ comprises implanting, with a Shannon-implant beam at a planetary Shannon-implant tilt angle (SITA) with respect to the Z-axis, the ESIR into the SCTZ.

7. The method of claim 6 wherein the planetary SITA is from about 7 degrees to about 15 degrees.

8. The method of claim 1 wherein forming the metal layer comprises depositing titanium/titanium nitride (Ti/TiN), forming a titanium silicide and filling the metal layer.