Gate length independent silicon-on-nothing (SON) scheme for bulk FinFETs

• US 9,006,077 B2
• Filed: 08/21/2013
• Issued: 04/14/2015
• Est. Priority Date: 08/21/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Akarvardar, Murat Kerem, Jacob, Ajey Poovannummoottil
• Primary Examiner(s): KUSUMAKAR, KAREN M
• Application Number:
  US13/971,937
• Publication Number:
  US 20150056781A1
• Time in Patent Office: 601 Days
• Field of Search: 438/156, 438/413, 438/421, 438/422
• US Class Current: 438/421
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Methods for fabricating integrated circuits and FinFET transistors on bulk substrates with active channel regions isolated from the substrate with an insulator are provided. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes forming fin structures overlying a semiconductor substrate, wherein each fin structure includes a channel material and extends in a longitudinal direction from a first end to a second end. The method deposits an anchoring material over the fin structures. The method includes recessing the anchoring material to form trenches adjacent the fin structures, wherein the anchoring material remains in contact with the first end and the second end of each fin structure. Further, the method forms a void between the semiconductor substrate and the channel material of each fin structure with a gate length independent etching process, wherein the channel material of each fin structure is suspended over the semiconductor substrate.

Claims

1. A method for fabricating a FinFET transistor, the method comprising:

forming fin structures overlying a semiconductor substrate, wherein each fin structure includes a channel material and extends in a longitudinal direction from a first end to a second end;

depositing an anchoring material over the fin structures;

recessing the anchoring material to form a lower trench surface bounding trenches adjacent the fin structures, wherein the anchoring material remains in contact with the first end and the second end of each fin structure; and

forming a void between the semiconductor substrate and the channel material of each fin structure with a gate length independent etching process, wherein the channel material of each fin structure is suspended over the semiconductor substrate, and wherein each void is bounded by a lower void surface that is positioned above the lower trench surface of the anchoring material.

2. The method of claim 1 wherein each void is bounded by an upper void surface and wherein the method further comprises:

depositing a dielectric material over the semiconductor substrate, wherein the dielectric material is deposited in the void to create an isolation block under the channel material in each fin structure and is deposited between adjacent fin structures;

recessing the dielectric material between adjacent fin structures to a lowered surface, wherein the lowered surface of the dielectric material is positioned above the upper void surface of each void.

3. The method of claim 1 wherein each void is bounded by an upper void surface and wherein the method further comprises:

depositing a dielectric material over the semiconductor substrate, wherein the dielectric material is deposited in the void to create an isolation block under the channel material in each fin structure and is deposited between adjacent fin structures;

recessing the dielectric material between adjacent fin structures to a lowered surface, wherein the lowered surface of the dielectric material is positioned below the upper void surface of each void.

4. The method of claim 1 further comprising:

depositing a dielectric material between adjacent fin structures and in the void to create an isolation block under the channel material in each fin structure; and

recessing the dielectric material between adjacent fin structures to expose a side surface of each isolation block.

5. A method for fabricating an integrated circuit, the method comprising:

forming fin structures overlying a semiconductor substrate, wherein each fin structure includes a channel material;

depositing a first dielectric material between the fin structures;

removing non-selected fin structures from the semiconductor substrate to form a gap between the first dielectric material adjacent a first selected fin structure and the first dielectric material adjacent a second selected fin structure;

depositing a shallow trench isolation material in the gap;

recessing the first dielectric material to form trenches between adjacent fin structures, between the first selected fin structure and the shallow trench isolation material, and between the second selected fin structure and the shallow trench isolation material;

forming a void between the channel material and semiconductor substrate in each fin structure to isolate the channel material; and

forming a gate structure overlying the fin structure after forming the void.

6. The method of claim 5 further comprising filling each void with a second dielectric material to create an isolation block under the channel material before forming the gate structure.

7. The method of claim 5 wherein each void is bounded by an upper void surface, and wherein the method further comprises:

depositing a second dielectric material over the semiconductor substrate, wherein the second dielectric material is deposited in the voids to create an isolation block under the channel material in each fin structure and is deposited in the trenches; and

recessing the dielectric material in the trenches to a lowered surface, wherein the lowered surface of the dielectric material is positioned above the upper void surface of each void.

8. The method of claim 5 further comprising:

depositing a second dielectric material over the semiconductor substrate, wherein the dielectric material is deposited in each void to create an isolation block under the channel material in each fin structure and is deposited between adjacent fin structures; and

recessing the dielectric material between adjacent fin structures to expose a side surface of each isolation block.

9. The method of claim 5 wherein:

recessing the first dielectric material comprises recessing the first dielectric material to form a lower trench surface bounding the trenches; and

forming the void between the channel material and the semiconductor substrate in each fin structure comprises bounding each void by a lower void surface that is positioned above the lower trench surface of the first dielectric material.

10. The method of claim 5 wherein each void is bounded by an upper void surface and wherein the method further comprises:

depositing a second dielectric material over the semiconductor substrate, wherein the second dielectric material is deposited in each void to create an isolation block under the channel material in each fin structure and is deposited between adjacent fin structures;

recessing the dielectric material between adjacent fin structures to a lowered surface, wherein the lowered surface of the dielectric material is positioned below the upper void surface of each void.

11. A method for fabricating an integrated circuit, the method comprising:

forming a fin structure overlying a semiconductor substrate, wherein the fin structure includes an underlying layer having sidewalls, a sacrificial layer having sidewalls and overlying the underlying layer, and a channel material overlying the sacrificial layer, and wherein the fin structure is positioned between a first trench and a second trench;

depositing an anchoring material in the first trench and in the second trench;

recessing the anchoring material to a lower trench surface to expose the sidewalls of the sacrificial layer and a portion of the sidewalls of the underlying layer;

etching through the sidewalls of the sacrificial layer and forming a void in the fin structure between the channel material and the semiconductor substrate;

depositing a dielectric material in the void to create an isolation block under the channel material, wherein the isolation block has sidewalls; and

forming a gate structure overlying the fin structure and in direct contact with the sidewalls of the isolation block.

12. The method of claim 11 wherein the void is bounded by a lower void surface that is positioned above the lower trench surface of the anchoring material.

13. The method of claim 11 wherein forming a fin structure overlying a semiconductor substrate comprises:

epitaxially growing the sacrificial layer over the semiconductor substrate, wherein the sacrificial layer is SiGe;

epitaxially growing the channel material over the sacrificial layer, wherein the channel material is silicon; and

etching trenches into the channel material and the sacrificial layer to form the fin structure; and

wherein depositing a dielectric material in the void comprises depositing oxide in the void.

14. The method of claim 11 wherein forming a fin structure overlying a semiconductor substrate comprises forming a fin structure extending along a longitudinal axis from a first end to a second end, and wherein the method further comprises supporting the fin structure at the first end and the second end while etching through the sidewalls of the sacrificial layer and forming a void in the fin structure between the channel material and the semiconductor substrate.

15. The method of claim 11 wherein:

the void is bounded by a lower surface of the channel material;

depositing the dielectric material in the void comprises depositing the dielectric material in the first trench and in the second trench;

the method further comprises recessing the dielectric material in the first trench and the second trench to a lowered surface; and

the lowered surface is positioned below the lower surface of the channel material.

16. The method of claim 11 wherein depositing the dielectric material in the void comprises depositing the dielectric material in the first trench and in the second trench, and wherein the method further comprises recessing the dielectric material in the first trench and the second trench to expose sidewalls of the isolation block.

17. The method of claim 11 wherein:

forming a fin structure overlying a semiconductor substrate comprises forming fin structures overlying the semiconductor substrate, wherein each fin structure includes an underlying layer having sidewalls, a sacrificial layer having sidewalls and overlying the underlying layer, and a channel material overlying the sacrificial layer, and wherein each fin structure is positioned between trenches;

depositing the anchoring material in the first trench and in the second trench comprises depositing the anchoring material in the trenches;

etching through the sidewalls of the sacrificial layer comprises etching through the sidewalls of the sacrificial layer in each fin structure and forming a void in each fin structure between the channel material and the semiconductor substrate; and

depositing a dielectric material in the void comprises depositing a dielectric material between the fin structures and in the void in each fin structure to create an isolation block under the channel material in each fin structure; and

the method further comprises;

removing non-selected fin structures from the semiconductor substrate to form a gap between the anchoring material adjacent a first selected fin structure and the anchoring material adjacent a second selected fin structure; and

depositing a shallow trench isolation material in the gap, wherein recessing the anchoring material comprises recessing the anchoring material between adjacent fin structures, between the first selected fin structure and the shallow trench isolation material, and between the second selected fin structure and the shallow trench isolation material.

18. The method of claim 11 wherein:

the void is bounded by a lower surface of the channel material;

depositing the dielectric material in the void comprises depositing the dielectric material in the first trench and in the second trench;

the method further comprises recessing the dielectric material in the first trench and the second trench to a lowered surface; and

the lowered surface is positioned above the lower surface of the channel material.

19. The method of claim 11 wherein forming a fin structure overlying a semiconductor substrate comprises forming selected fin structures and non-selected fin structures overlying the semiconductor substrate, wherein each fin structure includes an underlying layer having sidewalls, a sacrificial layer having sidewalls and overlying the underlying layer, and a channel material overlying the sacrificial layer, wherein depositing the anchoring material comprises depositing the anchoring material adjacent each fin structure;

and wherein the method further comprises;

removing the non-selected fin structures and the anchoring material between the non-selected fin structures to form a gap; and

depositing isolation material in the gap.