Semiconductor structure having fluoride metal layer and process thereof

• US 9,006,092 B2
• Filed: 11/03/2011
• Issued: 04/14/2015
• Est. Priority Date: 11/03/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lin, Kun-Hsien, Lin, Chun-Hsien, Huang, Hsin-Fu
• Primary Examiner(s): Moore, Whitney T
• Assistant Examiner(s): GALVIN III, JOSEPH M
• Application Number:
  US13/288,041
• Publication Number:
  US 20130113053A1
• Time in Patent Office: 1,258 Days
• US Class Current: 438/591
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A semiconductor structure includes a substrate, a dielectric layer and a fluoride metal layer. The dielectric layer is located on the substrate. The fluoride metal layer is located on the dielectric layer. Furthermore, the present invention also provides a semiconductor process to form said semiconductor structure.

Claims

1. A semiconductor structure, comprising:

a substrate;

a dielectric layer located on the substrate;

a fluoride metal layer located on the dielectric layer; and

a fluoride metal gate layer located on and directly contacting the fluoride metal layer.

2. The semiconductor structure according to claim 1, wherein the dielectric layer comprises a dielectric layer having a high dielectric constant.

3. The semiconductor structure according to claim 2, wherein the dielectric layer having a high dielectric constant further comprises a hafnium oxide (HfO2) layer.

4. The semiconductor structure according to claim 1, wherein the dielectric layer having a high dielectric constant comprises a fluoride dielectric layer having a high dielectric constant.

5. The semiconductor structure according to claim 1, wherein the fluoride metal layer comprises a fluoride work function metal layer.

6. The semiconductor structure according to claim 1, wherein the fluoride metal layer comprises a fluoride titanium nitride layer.

7. The semiconductor structure according to claim 1, wherein a work function value of the semiconductor structure is between 4.9 eV and 5.1 eV.

8. The semiconductor structure according to claim 1, wherein the semiconductor structure comprises a PMOS transistor.

15. The semiconductor structure according to claim 1, further comprising a barrier layer comprising a fluoride tantalum nitride layer located between the dielectric layer and the fluoride metal layer.

16. The semiconductor structure according to claim 1, wherein the dielectric layer comprises a hafnium silicon oxynitride (HfSiON) layer.

17. The semiconductor structure according to claim 1, wherein the fluoride metal layer has a U-shaped cross-sectional profile.

9. A semiconductor process, comprising:

providing a substrate;

forming a dielectric layer on the substrate;

forming a fluoride metal layer on the dielectric layer, wherein the fluoride metal layer is formed by an atomic layer deposition (ALD) process with a precursor of fluoride comprising titanium tetrafluoride (TiF4); and

forming a fluoride metal gate layer directly on the fluoride metal layer.

10. The semiconductor process according to claim 9, wherein the dielectric layer comprises a dielectric layer having a high dielectric constant.

11. The semiconductor process according to claim 9, wherein the fluoride metal layer comprises a fluoride work function metal layer.

12. The semiconductor process according to claim 9, wherein the fluoride metal layer comprises a fluoride titanium nitride layer.

13. The semiconductor process according to claim 9, wherein forming the fluoride metal layer comprises:

forming a metal layer on the dielectric layer; and

doping the metal layer with fluoride ions to form the fluoride metal layer.

14. The semiconductor process according to claim 9, wherein a barrier layer is formed on the dielectric layer after the dielectric layer is formed.