Thin film transistor array panel
First Claim
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1. A thin film transistor array panel comprising:
- a substrate;
a gate conductor comprising a lower layer disposed on the substrate and an upper layer disposed on the lower layer;
a first electrode disposed on the substrate;
a gate insulating layer disposed on the gate conductor and the first electrode;
a semiconductor disposed on the gate insulating layer;
a source electrode and a drain electrode disposed on the semiconductor;
a passivation layer disposed on the source electrode and the drain electrode; and
a second electrode disposed on the passivation layer,wherein, the lower layer of the gate conductor and the first electrode are disposed directly on the same layer and comprise the same type of material, andwherein the lower layer of the gate conductor and the first electrode comprise indium tin oxide (ITO) or indium zinc oxide (IZO), andwherein the upper layer of the gate conductor comprises copper or a copper alloy.
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Abstract
A manufacturing method of a thin film transistor array panel includes: simultaneously forming a gate conductor and a first electrode on a substrate, using a non-peroxide-based etchant; forming a gate insulating layer on the gate conductor and the first electrode; forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer; forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and forming a second electrode layer on the passivation layer.
8 Citations
7 Claims
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1. A thin film transistor array panel comprising:
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a substrate; a gate conductor comprising a lower layer disposed on the substrate and an upper layer disposed on the lower layer; a first electrode disposed on the substrate; a gate insulating layer disposed on the gate conductor and the first electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; a passivation layer disposed on the source electrode and the drain electrode; and a second electrode disposed on the passivation layer, wherein, the lower layer of the gate conductor and the first electrode are disposed directly on the same layer and comprise the same type of material, and wherein the lower layer of the gate conductor and the first electrode comprise indium tin oxide (ITO) or indium zinc oxide (IZO), and wherein the upper layer of the gate conductor comprises copper or a copper alloy. - View Dependent Claims (2, 3, 4)
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5. A thin film transistor array panel comprising:
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a substrate; a gate conductor comprising a lower layer disposed on the substrate and an upper layer disposed on the lower layer; a pixel electrode disposed on the substrate; a gate insulating layer disposed on the gate conductor and the pixel electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; a passivation layer disposed on the source electrode and the drain electrode; and a reference electrode disposed on the passivation layer, wherein, the lower layer of the gate conductor and the pixel electrode are disposed directly on the same layer and comprise the same type of material. - View Dependent Claims (6, 7)
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Specification