Semiconductor device and method for manufacturing thereof

• US 9,006,803 B2
• Filed: 04/13/2012
• Issued: 04/14/2015
• Est. Priority Date: 04/22/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Isobe, Atsuo, Sasaki, Toshinari, Sasagawa, Shinya, Ishizuka, Akihiro
• Primary Examiner(s): SHINGLETON, MICHAEL B
• Application Number:
  US13/446,028
• Publication Number:
  US 20120267624A1
• Time in Patent Office: 1,096 Days
• Field of Search: 257/288, 257/289, 257/410, 257/368, 257/255, 257/213, 257/43, 257/59, 257/72, 257/E29.117, 257/E29.137
• US Class Current: 257/288
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An insulating layer is provided with a projecting structural body, and a channel formation region of an oxide semiconductor layer is provided in contact with the projecting structural body, whereby the channel formation region is extended in a three dimensional direction (a direction perpendicular to a substrate). Thus, it is possible to miniaturize a transistor and to extend an effective channel length of the transistor. Further, an upper end corner portion of the projecting structural body, where a top surface and a side surface of the projecting structural body intersect with each other, is curved, and the oxide semiconductor layer is formed to include a crystal having a c-axis perpendicular to the curved surface.

Claims

1. A semiconductor device comprising:

an insulating layer, the insulating layer including a projecting portion;

an oxide semiconductor layer over the insulating layer;

a gate insulating layer over the oxide semiconductor layer; and

a gate electrode over the gate insulating layer,

wherein the oxide semiconductor layer faces to a side surface of the projecting portion, a top surface of the projecting portion, and a rounded surface of the projecting portion between the side surface and the top surface, and

wherein the oxide semiconductor layer includes a crystal having a c-axis substantially perpendicular to the rounded surface.

2. The semiconductor device according to claim 1, wherein the rounded surface has a radius of curvature greater than or equal to 20 nm and less than or equal to 60 nm.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes an In—

Ga—

Zn—

O based oxide semiconductor.

4. The semiconductor device according to claim 1, wherein the gate electrode faces to the side surface with the gate insulating layer interposed therebetween.

5. The semiconductor device according to claim 1, wherein the projecting portion has a tapered shape.

6. A semiconductor device comprising:

an insulating layer including a projecting structural body;

an oxide semiconductor layer in contact with at least a part of a top surface and a side surface of the projecting structural body;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode over the gate insulating layer, wherein the gate electrode covers at least a part of the top and the side surfaces of the projecting structural body; and

a source electrode and a drain electrode which are electrically connected to the oxide semiconductor layer,

wherein the projecting structural body has a rounded surface in an upper end corner portion where the top surface and the side surface intersect with each other, and

wherein the oxide semiconductor layer in the upper end corner portion includes a crystal having a c-axis substantially perpendicular to the rounded surface of the upper end corner portion.

7. The semiconductor device according to claim 6, wherein the rounded surface of the upper end corner portion has a radius of curvature greater than or equal to 20 nm and less than or equal to 60 nm.

8. The semiconductor device according to claim 6, wherein the oxide semiconductor layer includes a crystal having a c-axis substantially perpendicular to a surface of the insulating layer.

9. The semiconductor device according to claim 6, wherein an average surface roughness of the rounded surface is greater than or equal to 0.1 nm and less than 0.5 nm.

10. The semiconductor device according to claim 6, wherein an average surface roughness of a surface of the insulating layer is greater than or equal to 0.1 nm and less than 0.5 nm.