Trench-gate RESURF semiconductor device and manufacturing method

• US 9,006,822 B2
• Filed: 10/24/2012
• Issued: 04/14/2015
• Est. Priority Date: 12/07/2011
• Status: Active Grant

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Peake, Steven Thomas, Rutter, Phil
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): Hoque, Mohammad M
• Application Number:
  US13/659,678
• Publication Number:
  US 20130146967A1
• Time in Patent Office: 902 Days
• Field of Search: 257/329, 257/330, 257/341, 257/492, 257/493, 257/E29.257
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench-gate device with lateral RESURF pillars has an additional implant beneath the gate trench. The additional implant reduces the effective width of the semiconductor drift region between the RESURF pillars, and this provides additional gate shielding which improves the electrical characteristics of the device.

Claims

1. A trench-gate semiconductor device, comprising:

a drain contact;

a silicon semiconductor body over the drain contact which is doped with a first type of dopant;

a gate trench formed in a top portion of the semiconductor body;

a gate dielectric lining the gate trench;

a gate electrode formed in the gate trench;

source regions formed in the semiconductor body on opposite sides of the gate trench, separated from the gate electrode by the gate dielectric; and

an implant well on each side of the gate trench, doped with a second type of dopant, of opposite polarity type to the first type of dopant of the semiconductor body, and extending more deeply into the semiconductor body than the gate trench,

wherein the device further comprises

a pillar region extending downwardly from a bottom of the gate trench and which is electrically connected to the source regions, doped with the second type of dopant beneath the gate trench between the implant wells, and

an additional implant well connected to the source regions and to the pillar region and configured and arranged to bias the pillar region at a potential of the source regions.

2. A device as claimed in claim 1, further comprising:

a contact region to the source regions, comprising a moat formed around the source regions extending into the top portion of the semiconductor body, wherein the additional implant well is further configured to electrically connect the pillar region to the source regions.

3. A device as claimed in claim 1, wherein the pillar region has a width of between 0.7 and 1.0 times the width of the gate trench.

4. A device as claimed in claim 1, wherein the pillar region extends to a depth which is substantially equal to the depth of the implant wells.

5. A device as claimed in claim 1, wherein the semiconductor body is doped n-type, the implant wells and the pillar region are doped p-type.

6. A device as claimed in claim 1, wherein the additional implant connects the pillar region to the implant well.

7. A device as claimed in claim 6, wherein the additional implant is provided at ends of the gate trench and comprises the second type of dopant.

8. The device of claim 1 further comprising:

a moat in the top portion of the semiconductor body, above the implant well and both around and laterally outside the source regions, and

a contact region in the moat and connected to the source regions.

9. The device of claim 1, wherein the additional implant well configured and arranged to electrically connect the pillar region to the implant well on each side of the gate trench, wherein the gate dielectric is configured and arranged to isolate the gate trench from the source region.

10. The device of claim 1, wherein the gate dielectric includes a first portion lining side walls of the gate trench and having a first thickness, and a second portion lining the bottom of the gate trench and having a second thickness that is larger than the first thickness.

11. The device of claim 1, wherein the additional implant well electrically connects the pillar region to the source region.

12. The device of claim 1, wherein the additional implant well extends under the gate trench.