Power semiconductor device with reduced on-resistance and increased breakdown voltage

• US 9,006,824 B2
• Filed: 04/10/2014
• Issued: 04/14/2015
• Est. Priority Date: 05/13/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Henson, Timothy D.
• Primary Examiner(s): Pham, Long
• Application Number:
  US14/249,725
• Publication Number:
  US 20140332879A1
• Time in Patent Office: 369 Days
• Field of Search: 257/330, 257/327, 257/329
• US Class Current: 257/330
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one implementation, a power semiconductor device includes an active region and a termination region. A depletion trench finger extends from the active region and ends in the termination region. An arched depletion trench surrounds the depletion trench finger in the termination region, the arched depletion trench enables one or both of an increased breakdown voltage and a reduced on-resistance in the power semiconductor device.

Claims

1. A power semiconductor device comprising:

an active region and a termination region;

a depletion trench finger extending from said active region and ending in said termination region;

an arched depletion trench surrounding said depletion trench finger in said termination region, wherein said arched depletion trench enables at least one of an increased breakdown voltage and a reduced on-resistance in said power semiconductor device.

2. The power semiconductor device of claim 1, wherein a first distance between a side of said depletion trench finger and said arched depletion trench in said active region varies by less than approximately twenty percent (20%) from a second distance between a tip of said depletion trench finger and said arched depletion trench in said termination region.

3. The power semiconductor device of claim 1, wherein said power semiconductor device comprises a plurality of depletion trench fingers including said depletion trench finger, said arched depletion trench being a continuous trench configured to surround each of said plurality of depletion trench fingers.

4. The power semiconductor device of claim 1, wherein said power semiconductor device is a group IV power semiconductor device.

5. The power semiconductor device of claim 1, wherein said depletion trench finger and said arched depletion trench include respective buried depletion electrodes disposed therein.

6. The power semiconductor device of claim 1, wherein said power semiconductor device is a power MOSFET.

7. The power semiconductor device of claim 6, wherein said power MOSFET comprises a conductive substrate having a first conductivity type, a drift region having said first conductivity type formed over said conductive substrate, and a channel layer having a second conductivity type formed over said drift region.

8. The power semiconductor device of claim 6, wherein said depletion trench finger and said arched depletion trench extend from a surface of a channel layer having a second conductivity type into a drift region having a first conductivity type.

9. The power semiconductor device of claim 6, wherein said power MOSFET is a silicon MOSFET having a gate trench, a source, and a drain formed in said active region.

10. The power semiconductor device of claim 9, wherein each of said depletion trench finger and said arched depletion trench is substantially deeper than said gate trench.

11. The power semiconductor device of 9, wherein each of said depletion trench finger and said arched depletion trench includes a respective buried depletion electrode, each of said respective buried depletion electrodes being shorted to said source.

12. A power semiconductor device comprising:

an active region and a termination region;

a depletion trench finger extending from said active region and ending in said termination region;

an arched depletion trench surrounding said depletion trench finger in said termination region;

wherein a first distance between a side of said depletion trench finger and said arched depletion trench in said active region is substantially equal to a second distance between a tip of said depletion trench finger and said arched depletion trench in said termination region.

13. The power semiconductor device of claim 12, wherein said power semiconductor device comprises a plurality of depletion trench fingers including said depletion trench finger, said arched depletion trench being a continuous trench configured to surround each of said plurality of depletion trench fingers.

14. The power semiconductor device of claim 12, wherein said power semiconductor device is a group IV power semiconductor device.

15. The power semiconductor device of claim 12, wherein said depletion trench finger and said arched depletion trench include respective buried depletion electrodes disposed therein.

16. The power semiconductor device of claim 12, wherein said power semiconductor device is a power MOSFET.

17. The power semiconductor device of claim 12, wherein said power semiconductor device comprises a conductive substrate having a first conductivity type, a drift region having said first conductivity type formed over said conductive substrate, and a channel layer having a second conductivity type formed over said drift region.

18. The power semiconductor device of claim 12, wherein said power semiconductor device is a silicon MOSFET having a gate trench, a source, and a drain formed in said active region.

20. The power semiconductor device of claim 18, wherein each of said depletion trench finger and said arched depletion trench is substantially deeper than said gate trench.

19. The power semiconductor device of 18, wherein each of said depletion trench finger and said arched depletion trench includes a respective buried depletion electrode disposed therein, each of said respective buried depletion electrodes being shorted to said source.