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Method and structure for controlling stress in a transistor channel

  • US 9,006,836 B2
  • Filed: 04/17/2008
  • Issued: 04/14/2015
  • Est. Priority Date: 01/16/2004
  • Status: Active Grant
First Claim
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1. A semiconductor device, comprising:

  • a strain layer formed over n-type transistors and p-type transistors formed on a silicon substrate; and

    a first shallow-trench-isolation oxide around each of the n-type transistors and a second shallow-trench-isolation oxide around each of the p-type transistors,wherein an upper surface of the first shallow-trench-isolation oxide of the n-type transistors is at a level different than a level of an upper surface of the second shallow-trench-isolation oxide of the p-type transistors.

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