Method and structure for controlling stress in a transistor channel

• US 9,006,836 B2
• Filed: 04/17/2008
• Issued: 04/14/2015
• Est. Priority Date: 01/16/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Haining S., Zhu, Huilong
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): PRASAD, NEIL R
• Application Number:
  US12/104,526
• Publication Number:
  US 20080217696A1
• Time in Patent Office: 2,553 Days
• Field of Search: 257/E21.548, 257/288, 257/510, 257/374, 257/301, 438/427, 438/296, 438/199, 438/401, 438/211, 438/424, 438/221
• US Class Current: 257/369
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI

Abstract

A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves forming a shallow-trench-isolation oxide (STI) isolating the n-type device from the p-type device. The method further involves adjusting the shallow-trench-isolation oxide corresponding to at least one of the n-type device and the p-type device such that a thickness of the shallow-trench-isolation oxide adjacent to the n-type device is different from a thickness of the shallow-trench-isolation oxide adjacent to the p-type device, and forming a strain layer over the semiconductor substrate.

Claims

1. A semiconductor device, comprising:

a strain layer formed over n-type transistors and p-type transistors formed on a silicon substrate; and

a first shallow-trench-isolation oxide around each of the n-type transistors and a second shallow-trench-isolation oxide around each of the p-type transistors,

wherein an upper surface of the first shallow-trench-isolation oxide of the n-type transistors is at a level different than a level of an upper surface of the second shallow-trench-isolation oxide of the p-type transistors.

2. The device of claim 1, wherein the strain layer comprises a compressive strain layer.

3. The device of claim 2, wherein the upper surface of the first shallow-trench-isolation oxide of the n-type transistor is higher than an upper surface of the silicon substrate.

4. The device of claim 3, wherein the upper surface of the first shallow-trench-isolation oxide of the n-type transistor is about 300 Angstroms to about 1000 Angstroms higher than the upper surface of the silicon substrate.

5. The device of claim 4, wherein the upper surface of the second shallow-trench-isolation oxide of the p-type transistor is between being substantially planar to the upper surface of the silicon substrate to about 1000 Angstroms below the upper surface of the silicon substrate.

6. The device of claim 1, wherein the strain layer comprises a tensile strain layer.

7. The device of claim 6, wherein the upper surface of the second shallow-trench-isolation oxide of the p-type transistor is higher than an upper surface of the silicon substrate.

8. The device of claim 7, wherein the upper surface of the second shallow-trench-isolation oxide of the p-type transistor is about 300 Angstroms to about 1000 Angstroms higher than the upper surface of the silicon substrate.

9. The device of claim 8, wherein the upper surface of the first shallow-trench-isolation oxide of the n-type transistor is between being substantially planar to the upper surface of the silicon substrate to about 1000 Angstroms below the upper surface of the silicon substrate.

10. The device of claim 1, wherein the strain layer has a thickness of about 250 Angstroms to about 1500 Angstroms.

11. The device of claim 1, wherein compressive stresses of about 100 MPa to about 3 GPa exist within the channel of the p-type transistor.

12. The device of claim 1, wherein tensile stresses of about 100 MPa to about 3 GPa exist within the channel of the n-type transistor.

13. The device of claim 1, wherein the first shallow-trench-isolation oxide of each of the n-type transistor and the second shallow-trench-isolation oxide of each of the p-type transistor is about 200 Angstroms to about 1500 Angstroms from a corresponding gate of the n-type transistor or a corresponding gate of the p-type transistor, respectively.

14. The device of claim 1, wherein the strain layer comprises an etch stop nitride film.

15. The device of claim 14, further comprising a boron-phospho silicate glass (BPSG) layer formed on the etch stop nitride film.

16. The device of claim 1, wherein the first shallow-trench-isolation oxide around each of the n-type transistors are at different locations on the semiconductor device from that of the second shallow-trench-isolation oxide around each of the p-type transistors.

17. The device of claim 1, wherein:

the first shallow-trench-isolation oxide of each of the n-type transistors and the second shallow-trench-isolation oxide of each of the p-type transistors is a predetermined distance of about 200 Angstroms to about 1500 Angstroms from a corresponding gate of the n-type transistor or a corresponding gate of the p-type transistor, respectively, and

the predetermined distance of the first shallow-trench-isolation oxide is different from the predetermined distance of the second shallow-trench-isolation oxide.