Source/drain extension control for advanced transistors

• US 9,006,843 B2
• Filed: 02/24/2014
• Issued: 04/14/2015
• Est. Priority Date: 12/03/2010
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Ranade, Pushkar, Shifren, Lucian, Sonkusale, Sachin R.
• Primary Examiner(s): CHOI, CALVIN Y
• Application Number:
  US14/188,493
• Publication Number:
  US 20140167157A1
• Time in Patent Office: 414 Days
• Field of Search: 438/290, 257/368, 257/402
• US Class Current: 257/402
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10¹⁹ atoms/cm³, or alternatively, less than one-quarter the dopant concentration of the source and the drain.

Claims

1. A semiconductor die, comprising:

a plurality of transistors, the plurality of transistors each having;

a gate with an effective gate length;

a source region;

a drain region;

an epitaxially grown channel layer below the gate and extending between the source region and the drain region;

a first highly doped layer below the channel layer and coextensive therewith, the first highly doped layer effective to set a depletion depth for said plurality of transistors; and

wherein some of the plurality of transistors have a second highly doped layer below the channel layer and above the first highly doped layer;

wherein some of the plurality of transistors include a source and drain extension region; and

wherein some of the plurality of transistors are haloless.

2. A semiconductor die as in claim 1, wherein the first highly doped layer has a dopant concentration of between 5×

10¹⁸ to 1×

10²⁰ atoms/cm³.

3. A semiconductor die as in claim 1, wherein the second highly doped layer has a dopant concentration of between 1×

10¹⁸ to 1×

10¹⁹ atoms/cm³.

4. A semiconductor die as in claim 1, wherein some of the plurality of transistors have another highly doped layer below the first highly doped layer and coextensive therewith, the another highly doped layer effective to function as a punch through suppression layer.

5. A semiconductor die as in claim 1, wherein the epitaxially grown channel layer is undoped.

6. A semiconductor die as in claim 1, wherein the source and drain extensions are formed by ion implantation.

7. A semiconductor die as in claim 1, wherein the source region and the drain region are formed by ion implantation.

8. A semiconductor die as in claim 1, wherein the source region and the drain region are formed by selective epitaxial growth.

9. A semiconductor die as in claim 1, wherein the source region and the drain region are raised.

10. A semiconductor die as in claim 1, wherein the second highly doped layer is formed on a substrate.

19. A semiconductor die as in claim 1, wherein the second highly doped layer has a dopant concentration of between 5×

10¹⁸ to 1×

10²⁰ atoms/cm³.

20. A semiconductor die as in claim 1, wherein the first highly doped layer has a dopant concentration of between 1×

10¹⁸ to 1×

10¹⁹ atoms/cm³.

11. A semiconductor structure on a bulk silicon substrate, the structure comprising:

a transistor having a gate, a source region and a drain region;

an undoped epitaxially grown channel layer below the gate and extending between the source region and the drain region;

a first highly doped layer below the channel layer, the highly doped layer extending laterally across the channel layer;

a second highly doped layer below the first highly doped layer and coextensive therewith, the second highly doped layer being doped to a concentration sufficient to set the depletion width for the transistor;

a third highly doped layer below the second highly doped layer and coextensive therewith, the third highly doped layer being doped to a concentration sufficient to serve as a punch through suppression layer; and

wherein the transistor is haloless.

12. A semiconductor structure as in claim 11, wherein the punch through suppression layer has a dopant concentration less than the second highly doped layer.

13. A semiconductor structure as in claim 11, wherein the first highly doped layer is coextensive with the channel layer.

14. A semiconductor structure as in claim 11, wherein the first highly doped layer and the second highly doped layers are separate distinct layers.

15. A semiconductor structure as in claim 11, wherein the source region and the drain region further include respective source and drain extensions.

16. A semiconductor structure as in claim 15, wherein the source and drain extensions are formed by ion implantation.

17. A semiconductor structure as in claim 11, wherein the source region and the drain region are formed by ion implantation.

18. A semiconductor structure as in claim 11, wherein the source region and the drain region are formed by selective epitaxial growth.