Process and structure for high temperature selective fusion bonding

• US 9,006,844 B2
• Filed: 01/26/2011
• Issued: 04/14/2015
• Est. Priority Date: 01/28/2010
• Status: Active Grant

• Current Assignee: Dunan Microstaq, Inc. (Zhejiang Dun'an Artificial Environment Co., Ltd.)
• Original Assignee: Dunan Microstaq, Inc. (Zhejiang Dun'an Artificial Environment Co., Ltd.)
• Inventors: Arunasalam, Parthiban
• Primary Examiner(s): GORDON, MATTHEW E
• Application Number:
  US13/574,343
• Publication Number:
  US 20120299129A1
• Time in Patent Office: 1,539 Days
• Field of Search: 257/415, 257/50, 257/678, 257/684, 257/704, 257/E21.211, 257/E29.324, 438/706, 438/710, 438/455
• US Class Current: 257/415
• CPC Class Codes: B81B 3/001 Structures having a reduced contact area, e.g. with bumps or with a textured surface
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/036 Fusion bonding

Abstract

A method to prevent movable structures within a MEMS device, and more specifically, in recesses having one or more dimension in the micrometer range or smaller (i.e., smaller than about 10 microns) from being inadvertently bonded to non-moving structures during a bonding process. The method includes surface preparation of silicon both structurally and chemically to aid in preventing moving structures from bonding to adjacent surfaces during bonding, including during high force, high temperature fusion bonding.

Claims

1. A method of selectively preparing a silicon surface for selective fusion bonding, comprising:

a) aligning a silicon surface and a shadow mask so as to create a masked area and an unmasked area of the silicon surface;

b) treating the unmasked area of the silicon surface to prevent fusion bonding, including depositing a layer of silicon nitride on the unmasked area of the silicon surface, wherein the silicon nitride is initially applied at a first deposition rate, and subsequently applied at a second deposition rate greater than the first deposition rate; and

c) removing the shadow mask from the silicon surface after the treatment in step b).

2. The method of claim 1, wherein the silicon surface is a silicon dioxide layer, and wherein before step b) the silicon dioxide layer is roughened.

3. The method of claim 2, wherein the silicon dioxide layer is roughened utilizing one of radiofrequency etching and reactive ion etching.

4. The method of claim 1, wherein the first deposition rate is less than about 25 Angstroms per minute.

5. The method of claim 1, wherein the second deposition rate is equal to or greater than about 25 Angstroms per minute.

6. The method of claim 1, wherein the silicon nitride is applied utilizing Plasma-Enhanced Chemical Vapor Deposition (PECVD).

7. The method of claim 1, wherein in step b) the silicon nitride is non-uniformly deposited, such that the general thickness of the silicon nitride layer varies from location to location within the area the silicon nitride is deposited.

8. The method of claim 1, wherein in a preliminary step prior to step a), native oxides are removed.

9. The method of claim 8, wherein

after the preliminary step and before step a) an oxide layer is formed on the silicon surface.

10. The method of claim 9, wherein the oxide layer is roughened prior to step b).

11. The method of claim 1, wherein prior to step a) a recess is formed in the silicon surface, the unmasked area of the silicon surface being disposed in the recess.

12. The method of claim 11, wherein before step a) an oxide layer is formed in the recess, including on at least a portion of the unmasked area.

13. The method of claim 12, wherein

step b) includes depositing the layer of silicon nitride on the unmasked area of the silicon surface in the recess;

and

the deposition of silicon nitride in step b) is terminated when the depth of the recess less the combined thickness of the silicon nitride layer formed in step b) and the oxide layer provides a desired clearance to an adjacent component when the adjacent component is disposed over the recess and supported by non-recessed portions of the silicon surface.

14. The method of claim 1, wherein

a recess is formed in the silicon surface, the unmasked area of the silicon surface being disposed in the recess;

step b) includes depositing a layer of silicon nitride on the unmasked area of the silicon surface in the recess; and

the deposition of nitride in step h) is terminated when the depth of the recess less the thickness of the silicon nitride layer formed in step h) provides a desired clearance to an adjacent component when the adjacent component is disposed over the recess and supported by the non-recessed portions of the silicon surface.

15. A method of selectively preparing a surface for selective fusion bonding, comprising:

a) aligning a silicon surface defining a recess and a shadow mask so as to create a masked area and an unmasked area of the silicon surface;

b) treating the unmasked area of the silicon surface to prevent fusion bonding, including non-uniformly depositing a layer of silicon nitride on the unmasked area of the silicon surface such that the general thickness of the silicon nitride layer varies from location to location within the area the silicon nitride is deposited and wherein the silicon nitride is deposited to form the silicon nitride layer in the recess such that the silicon nitride layer is generally thicker in a central portion of the recess, and thinner elsewhere; and

c) removing the shadow mask from the silicon surface after the treatment in step b).