Through silicon via with reduced shunt capacitance

• US 9,006,846 B2
• Filed: 09/20/2011
• Issued: 04/14/2015
• Est. Priority Date: 09/20/2010
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Bryzek, Janusz, Bloomsburgh, John Gardner, Acar, Cenk
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US13/821,612
• Publication Number:
  US 20130277773A1
• Time in Patent Office: 1,302 Days
• US Class Current: 257/415
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 2207/096 through the substrate
• CPC Class Codes: B81B 3/0086 Electrical characteristics, e.g. reducing driving voltage, improving resistance to peak voltage
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: H01G 7/06 having a dielectric selected for the variation of its permittivity with applied voltage, i.e. ferroelectric capacitors electrets H01G7/02

Abstract

This document refers to apparatus and methods for a device layer of a microelectromechanical system (MEMS) sensor having vias with reduced shunt capacitance. In an example, a device layer can include a substrate having a pair of trenches separated in a horizontal direction by a portion of the substrate, wherein each trench of the pair of trenches includes first and second vertical layers including dielectric, the first and second vertical layers separated by a third vertical layer including polysilicon.

Claims

1. A via layer for a MEMS device, the via layer comprising;

a substrate having a pair of trenches separated in a horizontal direction by a portion of the substrate, wherein each trench of the pair of trenches includes first and second vertical layers including a dielectric, the first and second vertical layers separated by a third vertical layer including polysilicon, wherein each of the first and second vertical layers include thermal oxide and a third material having a dielectric constant lower than the dielectric constant of the thermal oxide.

2. The via layer of claim 1, wherein less than about 80% of the volume of the third vertical layer includes polysilicon.

3. The via layer of claim 1, wherein less than about 20% of the volume of the third vertical layer includes polysilicon.

4. The via layer of claim 1, wherein the first and second vertical layers include thermal oxide.

5. A sensor comprising:

a cap layer;

a device layer, coupled to the cap layer, including a proof mass; and

a via layer coupled to the device layer, wherein the device layer includes;

a silicon substrate having a pair of trenches separated in a horizontal direction by a portion of the silicon substrate,

wherein each trench of the pair of trenches includes first and second vertical layers including a dielectric separated by a third vertical layer including polysilicon; and

wherein each of the first and second vertical layers include thermal oxide and a second material having a dielectric constant lower than the dielectric constant of the thermal oxide.

6. The sensor of claim 5, wherein less than about 80% of the volume of the third vertical layer includes polysilicon.

7. The sensor of claim 5, wherein less than about 20% of the volume of the third vertical layer includes polysilicon.

8. The sensor of claim 5, wherein the first and second vertical layers include thermal oxide.