Encapsulation of an MEMS component and a method for producing said component

• US 9,006,868 B2
• Filed: 11/18/2011
• Issued: 04/14/2015
• Est. Priority Date: 12/28/2010
• Status: Active Grant

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Epcos AG (TDK Corporation)
• Inventors: Bauer, Christian, Krger, Hans, Stelzl, Alois, Portmann, Jrgen
• Primary Examiner(s): HO, TU TU V
• Application Number:
  US13/976,420
• Publication Number:
  US 20130341773A1
• Time in Patent Office: 1,243 Days
• Field of Search: 257/659, 257/710, 257/711, 438/121
• US Class Current: 257/659
• CPC Class Codes: B81B 7/0064 for protecting against electromagnetic or electrostatic interferences
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/29 characterised by the material , e.g. carbon interlayer dielectrics H01L23/5329
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3142 Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H03H 3/02 for the manufacture of piezoelectric or electrostrictive resonators or networks H03H3/08 takes precedence
• CPC Class Codes: H03H 9/10 Mounting in enclosures constructional combinations of enclosure with electromechanical and other electronic elements H03H9/0538

Abstract

The invention relates to a component and a method for producing said component. The component comprises a substrate (S), a chip (CH), a frame (MF), which is connected to the substrate (S) and on which the chip (CH) bears. A metallic closure layer (ML) encompasses the frame (MF), the substrate (S) and the chip (CH) such that a volume enclosed by the substrate (S), the chip (CH) and the frame (MF) is hermetically sealed.

Claims

1. A method for producing a component comprising a substrate, a chip and a frame, comprising the following sequence of steps:

applying the frame to the substrate;

connecting the chip to the frame by placing the chip onto the frame; and

hermetically sealing a volume enclosed by the substrate, the chip and the frame by means of a metallic closure layer,

wherein the hermetic sealing by means of the metallic closure layer is effected by the metallic closure layer being applied on the frame and the chip over the whole area,

wherein the closure layer is applied by means of at least one of the following;

applying metal particles with a plasma jet,

spraying on metal particles dissolved in a solvent,

vapor deposition of one or a plurality of metal particles,

wherein after the metallic closure layer has been applied, the metallic closure layer is sintered.

3. The method according to claim 1, wherein the chip has electrically conductive structures on a side inclined toward the enclosed volume and is interconnected with the substrate by means of at least one bump connection.

4. The method according to claim 1 or 2, wherein the frame has a planar surface in such a way that the chip bears homogeneously on the frame.

5. The method according to claim 1 or 2, wherein the chip is a microelectromechanical system, a microelectro optical system, or a microelectro optomechanical system.

6. The method according to claim 1, wherein metal particles, in particular metallic nano or microparticles, are admixed with the plasma jet.

7. The method according to claim 1, wherein the metallic closure layer is reinforced by plating.

2. A method for producing a component comprising a substrate, a chip and a frame, comprising the following sequence of steps:

applying the frame to the substrate;

connecting the chip to the frame by placing the chip onto the frame; and

hermetically sealing a volume enclosed by the substrate, the chip and the frame by means of a metallic closure layer, the metallic closure layer being a multilayer metal foil,

wherein the metallic closure layer is applied to the frame and the chip by means of fusion of the multilayer metal foil with pressurization.