Active gate drive circuit

• US 9,007,102 B2
• Filed: 06/19/2014
• Issued: 04/14/2015
• Est. Priority Date: 06/20/2013
• Status: Active Grant

• Current Assignee: ABB Schweiz AG (ABB Limited)
• Original Assignee: ABB Research Ltd. (ABB Ltd.)
• Inventors: Lobsiger, Yanick, Kolar, Johann, Laitinen, Matti
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US14/309,171
• Publication Number:
  US 20140375362A1
• Time in Patent Office: 299 Days
• Field of Search: None
• US Class Current: 327/109
• CPC Class Codes: H03K 17/00 Electronic switching or gating, i.e. not by contact-making and –breaking gated amplifiers H03F3/72; switching arrangements for exchange systems using static devices H04Q3/52
• CPC Class Codes: H03K 17/166 Soft switching
• CPC Class Codes: H03K 17/168 in composite switches

Abstract

An exemplary gate drive circuit and method are disclosed for controlling a gate-controlled component, the gate drive circuit having a PI controller adapted to receive an input reference signal and to control a gate voltage of the gate-controlled component. The gate drive circuit can include a first feedback loop for the PI controller, the first feedback loop having a first gain (k_v), a second feedback loop for the PI controller, the second feedback loop having a second gain (k_i), and a clipping circuit adapted to modify a feedback signal in the second feedback loop during turn-on of the gate-controlled component when the time derivative of the collector current is negative. The first feedback loop can include a first blanking circuit adapted to cut the feedback loop when the gate-controlled component is in a blocking state.

Claims

1. A gate drive circuit for controlling a gate-controlled component, the gate drive circuit comprising:

a PI controller configured to receive an input reference signal (v_ref,d/dt) and to control a gate voltage of a gate-controlled component;

a first feedback loop for the PI controller configured to provide feedback from a time derivative of a collector-to-emitter voltage (v_CE) of the gate-controlled component, the first feedback loop having first gain (k_v), and having a first blanking circuit configured to cut the first feedback loop when the gate-controlled component is in a blocking state; and

a second feedback loop for the PI controller configured to provide feedback from a time derivative of a collector current (i_C) of the gate-controlled component, the second feedback loop having second gain (k_i), and having a clipping circuit configured to modify the feedback signal in the second feedback loop during turn-on of the gate-controlled component when the time derivative of the collector current is negative.

2. A gate drive circuit according to claim 1, comprising:

a gate current control loop configured to use the PI controller, which gate current control loop will receive a feedback signal from a gate current and is connectable to control gate current during turn-on and turn-off delays.

3. A gate drive circuit according to claim 1, comprising:

a buffer circuit (BUF) for amplifying an output signal from the PI controller to drive the gate-controlled component.

4. A gate drive circuit according to claim 1, wherein the clipping circuit comprises:

a controlled component for enabling the clipping circuit.

5. A gate drive circuit according to claim 1, wherein once enabled, the clipping circuit is configured to limit an output of the gate drive circuit.

6. A gate drive circuit according to claim 1, wherein the time derivative of the collector-to-emitter voltage is determined as a voltage level by a capacitor included in the first feedback loop, the capacitor being responsive to a collector-to-emitter voltage change.

7. A gate drive circuit according to claim 1 wherein the time derivative of the collector current is determined as a voltage level from a voltage over a known inductance.

8. A gate drive circuit according to claim 1, wherein the first feedback loop comprises:

a second blanking circuit configured to cut the first feedback loop when the controlled component is in the blocking state.

9. A gate drive circuit according to claim 8, wherein the first and/or second blanking circuit(s) is/are configured to receive control (v_ctrl,FB) for cutting the first feedback loop based on a status of the gate-controlled component or its gate.

10. A gate drive circuit according to claim 9, wherein the control for cutting the feedback loop is based on determining whether the gate voltage of the gate-controlled component is below a threshold voltage (V_ge,th).

11. A gate drive circuit according to claim 1, comprising:

a third feedback loop configured to provide feedback from a collector-to-emitter voltage (v_CE) of the gate-controlled component, the third feedback loop having a third gain (k_ov), and being configured to be operational to increase the gate voltage when the collector-to-emitter voltage of the gate-controlled component is above a set overvoltage limit value.

12. A gate drive circuit according to claim 9, in a half bridge configuration, wherein the control (v_ctrl,FB) for cutting the first feedback loop is configured for interlocking low side and high side controls to prevent cross conducting.

13. A gate drive circuit according to claim 1, in a half bridge configuration, wherein in case of over-current, the first blanking circuit is configured to deactivate the first feedback loop or the first and second feedback loops when a power semiconductor is in a state for short circuit turn-off at a set negative gate current.

15. A gate drive circuit according to claim 2, comprising:

a buffer circuit (BUF) for amplifying an output signal from the PI controller to drive the gate-controlled component.

16. A gate drive circuit according to claim 15, wherein the clipping circuit comprises:

a controlled component for enabling the clipping circuit.

17. A gate drive circuit according to claim 16, wherein once enabled, the clipping circuit is configured to limit an output of the gate drive circuit.

18. The gate drive circuit according to claim 7, wherein the inductance is a parasitic bonding wire inductance of an emitter.

19. A gate drive circuit according to claim 17, comprising:

a third feedback loop configured to provide feedback from a collector-to-emitter voltage (v_CE) of the gate-controlled component, the third feedback loop having a third gain (k_ov), and being configured to be operational to increase the gate voltage when the collector-to-emitter voltage of the gate-controlled component is above a set overvoltage limit value.

20. A gate drive circuit according to claim 19, in a half bridge configuration, wherein in case of over-current, the first blanking circuit is configured to deactivate the first feedback loop or the first and second feedback loops when a power semiconductor is in a state for short circuit turn-off at a set negative gate current.

14. A method for controlling a gate-controlled component by using a PI controller configured to receive an input reference signal (v_ref,d/dt) and to control a gate voltage of the gate-controlled component, the method comprising:

providing the input reference signal (v_ref,d/t) to the PI controller;

obtaining a first feedback signal for the PI controller in a first feedback loop from a time derivative of a collector-to-emitter voltage (v_CE) of the gate-controlled component;

obtaining a second feedback signal for the PI controller in a second feedback loop from a time derivative of a collector current (i_C) of the gate-controlled component;

modifying the second feedback signal in a second feedback loop during turn-on of the gate-controlled component when the time derivative of the collector current is negative; and

cutting the first feedback signal when the gate-controlled component is in a blocking state.