Semiconductor device including clock signal generation unit

• US 9,007,114 B2
• Filed: 01/15/2014
• Issued: 04/14/2015
• Est. Priority Date: 03/11/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Koo, Kyunghoi
• Primary Examiner(s): WELLS, KENNETH B
• Application Number:
  US14/155,692
• Publication Number:
  US 20140253178A1
• Time in Patent Office: 454 Days
• Field of Search: 327/291, 326/30, 365/193
• US Class Current: 327/291
• CPC Class Codes: H03K 5/02 by amplifying H03K5/04 takes precedence
• CPC Class Codes: H03K 5/24 the characteristic being amplitude

Abstract

A semiconductor device for stably generating a clock signal from a strobe signal includes a processor, a clock signal generation unit receiving a first strobe signal and a second strobe signal to generate the clock signal, and a data reception unit receiving at least one data signal to provide the received data signal to the processor. The clock signal generation unit may comprise a strobe comparator comparing a voltage of a first input terminal with that of a second input terminal to output logic high or logic low, a first switch selectively connecting one of a first and a second signal line to the first input terminal, a second switch selectively connecting one of the second signal line and a reference line to the second input terminal, and a voltage stabilizing circuit pulling up/down at least one of a voltage of the first and the second signal line.

Claims

1. A semiconductor device comprising:

a processor;

a clock signal generation unit to receive a first strobe signal and a second strobe signal to generate a clock signal to be provided to the processor; and

a data reception unit to receive at least one data signal to provide the received data signal to the processor,

wherein the clock signal generation unit comprises;

a strobe comparator to compare a voltage of a first input terminal with a voltage of a second input terminal to output logic high or logic low according to a result of comparison;

a first switch to selectively connect one of a first signal line by which the first strobe signal is transmitted and a second signal line by which the second strobe signal is transmitted, to the first input terminal;

a second switch to selectively connect one of the second signal line and a reference line to the second input terminal, the reference line being a line by which a reference voltage is transmitted from the data reception unit; and

a voltage stabilizing circuit to pull up or pull down at least one of a voltage of the first signal line and a voltage of the second signal line.

2. The semiconductor device of claim 1, wherein the strobe comparator outputs logic high or logic low when a difference between the voltage of the first input terminal and the voltage of the second input terminal is greater than a predetermined value.

3. The semiconductor device of claim 1, wherein the voltage stabilizing circuit comprises a termination pull-up/pull-down unit to pull up at least one of the voltage of the first signal line and the voltage of the second signal line through a termination pull-up resistor having a predetermined resistance value, or to pull down at least one of the voltage of the first signal line and the voltage of the second signal line through a termination pull-down resistor having a predetermined resistance value, and

wherein the termination pull-up/pull-down unit comprises a first pull-up switch to provide a pull-up voltage to the first signal line.

4. The semiconductor device of claim 3, wherein the termination pull-up/pull-down unit further comprises a first pull-down switch to provide a pull-down voltage to the first signal line, and

wherein the first pull-up switch and the first pull-down switch are complementarily turned on.

5. The semiconductor device of claim 3, wherein the second switch connects the second signal line to the second input terminal when the reference line is not connected to the second input terminal.

6. The semiconductor device of claim 5, wherein the first switch connects the first signal line to the first input terminal when the second signal line is connected to the second input terminal.

7. The semiconductor device of claim 6, wherein the termination pull-up/pull-down unit further comprises a second pull-up switch to provide a pull-up voltage to the second signal line.

8. The semiconductor device of claim 7, wherein the voltage stabilizing circuit controls turn-on/turn-off of the first pull-up switch and the second pull-up switch in response to a control signal provided from the processor.

9. The semiconductor device of claim 3, wherein the voltage stabilizing circuit further comprises a weak pull-up/pull-down unit pulling up at least one of the voltage of the first signal line and the voltage of the second signal line through a weak pull-up resistor having a different predetermined resistance value from the termination pull-up resistor, or pulling down at least one of the voltage of the first signal line and the voltage of the second signal line through a weak pull-down resistor having a different predetermined resistance value from the termination pull-down resistor.

10. The semiconductor device of claim 9, wherein the voltage stabilizing circuit pulls up or pulls down at least one of the voltage of the first signal line and the voltage of the second signal line by using one of the termination pull-up/pull-down unit and the weak pull-up/pull-down unit according to a predetermined operation mode.

11. The semiconductor device of claim 1, wherein the clock signal generation unit further comprises a strobe buffer to buffer an output of the strobe comparator to provide the buffered output to the processor as the clock signal.

12. The semiconductor device of claim 1, wherein the processor samples a data signal provided from the data reception unit, according to the clock signal.

13. A semiconductor device comprising:

a processor;

a clock signal generation unit to receive a first strobe signal and a second strobe signal to generate a clock signal to be provided to the processor; and

a data reception unit to receive at least one data signal to provide the received data signal to the processor,

wherein the clock signal generation unit comprises;

a strobe comparator to compare a voltage of a first input terminal with a voltage of a second input terminal to output logic high or logic low according to a result of comparison;

a first switch to selectively connect one of a first signal line and a reference line to the first input terminal, the first signal line being a first line by which the first strobe signal is transmitted, and the reference line being a second line by which a reference voltage is transmitted from the data reception unit;

a second switch to selectively connect one of a second signal line and the reference line to the second input terminal, the second signal line being a third line by which the second strobe signal is transmitted; and

a voltage stabilizing circuit to pull up or pull down at least one of a voltage of the first signal line and a voltage of the second signal line.

14. The semiconductor device of claim 13, wherein the clock signal generation unit controls the first switch and the second switch so that the reference line is connected to only one of the first input terminal and the second input terminal.

15. The semiconductor device of claim 13, wherein the voltage stabilizing circuit comprises a plurality of pull-up/pull-down units, and

wherein each of the plurality of pull-up/pull-down units includes pull-up resistor and pull-down resistor having different resistance values from the others, and pulls up or pulls down at least one of the voltage of the first signal line and the voltage of the second signal line by using one of the plurality of pull-up/pull-down units according to a predetermined operation mode.

16. A semiconductor device, comprising:

a clock signal generation unit configured to generate a clock signal based on a differential signal received as a strobe signal including a first strobe signal and a second strobe signal, the clock signal generation unit comprising;

a voltage stabilizing unit; and

a comparator having a first input terminal and a second input terminal and configured to output a high level or low level logic signal based on a comparison of voltage of each of signals received at the first and second input terminals;

a first switch configured to selectively transmit one of the first strobe signal, the second strobe signal, and a reference voltage signal to the first input terminal; and

a second switch configured to selectively transmit either the second strobe signal or the reference voltage signal to the second input terminal;

a processor configured to control operation of the voltage stabilizing unit,

wherein the voltage stabilizing unit comprises a first pull-up/pull-down unit configured to selectively pull up or pull down at least one of the first and second strobe signals to a high or low logic level through a first resistance, and a second pull-up/pull-down unit configured to selectively pull up or pull down at least one of the first and second strobe signals to a high or low logic level through a second resistance different from the first resistance.

17. The semiconductor device of claim 16, wherein the processor is configured to activate or deactivate the first pull-up/pull-down unit and/or the second pull-up/pull-down unit according to an operation frequency of the strobe signal.

18. The semiconductor device of claim 16, further comprising a data reception unit configured to receive at least one input data signal and to provide an output data signal to the processor.

19. The semiconductor device of claim 18, wherein the processor samples the output data signal provided from the data reception unit according to the clock signal.