Interface for communication between voltage domains

• US 9,007,141 B2
• Filed: 05/23/2012
• Issued: 04/14/2015
• Est. Priority Date: 05/23/2012
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Steeneken, Peter Gerard
• Primary Examiner(s): Takaoka, Dean
• Assistant Examiner(s): Wong, Alan
• Application Number:
  US13/478,737
• Publication Number:
  US 20130316646A1
• Time in Patent Office: 1,056 Days
• Field of Search: 333/24.C, 333/238, 307/109
• US Class Current: 333/24.C
• CPC Class Codes: H01G 4/06 Solid dielectrics
• CPC Class Codes: H01G 4/385 Single unit multiple capacitors, e.g. dual capacitor in one coil
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01P 1/04 Fixed joints
• CPC Class Codes: H03H 7/004 Capacitive coupling circuits not otherwise provided for
• CPC Class Codes: H04B 5/22 Capacitive coupling

Abstract

In one or more embodiments, circuitry is provided for isolation and communication of signals between circuits operating in different voltage domains using capacitive coupling. The capacitive coupling is provided by one or more capacitive structures having a breakdown voltage that is defined by way of the various components and their spacing. The capacitive structures each include three capacitive plates arranged to have two plates located in an upper layer and one plate located in a lower layer. A communication signal can be transmitted via the capacitive coupling created between the lower plate and each of the upper plates, respectively.

Claims

1. An isolation circuit comprising:

a first conducting substrate that is electrically connected to a reference voltage of a first voltage domain;

a second conducting substrate that is electrically connected to a reference voltage of a second voltage domain;

a first capacitive structure that is located on the first conducting substrate and in a first voltage domain, the first capacitive structure including

first input and output capacitor plates that share a first intermediate capacitor plate to function as two series capacitors;

a first dielectric layer configured and arranged to provide a first breakdown voltage by providing physical separation between the first intermediate capacitor plate and each of the first input and output capacitor plates, and

a second dielectric layer configured and arranged to provide substantially the same breakdown voltage as the first breakdown voltage, and a physical separation provided between the first conducting substrate and the first intermediate capacitor plate;

a second capacitive structure in a second voltage domain and that is located on the second conducting substrate and including,

second input and output capacitor plates that share a second intermediate capacitor plate to function as two series capacitors;

a third dielectric layer configured and arranged to provide a second breakdown voltage of the second capacitive structure by providing physical separation between the second intermediate plate and each of the second input and output plates, and

a fourth dielectric layer configured and arranged to provide substantially the same breakdown voltage as the second breakdown voltage and to provide physical separation provided between the second conducting substrate and the second intermediate plate; and

a current path between the first output capacitor plate and the second input capacitor plate.

2. The circuit of claim 1, wherein the each of the first and second conductive substrates includes a corresponding and respective handle wafer, silicon-based layer and buried oxide layer providing isolation between the handle wafer and the silicon layer and wherein the silicon layer is conductive and connected to the reference voltage of the respective and corresponding voltage domain.

3. The circuit of claim 1, wherein the reference voltages of the first and second voltage domains are ground voltages for the respective first and second voltage domains.

4. The circuit of claim 1, wherein the first and second dielectric layers are formed of the same dielectric material and have substantially the same thickness as the other and wherein the third and fourth dielectric layers are formed of the same dielectric material and have substantially the same thickness as the other.

5. A device comprising:

a transmitter circuit that is in a first voltage domain and that is configured and arranged to transmit communication signals;

a receiver circuit that is in a second voltage domain, and that has an input that is configured and arranged to receive the communication signals in the second voltage domain; and

an isolation circuit configured and arranged to provide capacitive isolation for the communication signals between the first and second voltage domains, the isolation circuit including

a first capacitive structure located on a first substrate in a first voltage domain and including

a first capacitive plate configured and arranged to receive the communication signals from the transmitter circuit and in the first voltage domain,

a second capacitive plate that is configured and arranged to receive the communication signals from the first capacitive plate at a first floating node of the isolation circuit,

a third capacitive plate that is configured and arranged to receive the communication signals from the second capacitive plate at a second floating node of the isolation circuit,

a first dielectric layer configured and arranged to provide first breakdown voltages of the first capacitive structure by providing an electrical and physical separation between the second capacitive plate and each of the first and third capacitive plates, the physical separation having a first distance, and

a second dielectric layer providing an electrical and physical separation between the first substrate and the second capacitive plate to provide substantially the same breakdown voltages as the first breakdown voltages;

a conductor providing a current path from an input connected to the third capacitive plate to an output; and

a second capacitive structure located on a second substrate in a second voltage domain and including,

a fourth capacitive plate connected to the conductor at the output of the current path and configured and arranged to receive the communication signals from the third capacitive plate by way of the current path;

a fifth capacitive plate configured and arranged to receive the communication signals from the fourth capacitive plate at a fourth floating node of the isolation circuit,

a sixth capacitive plate configured and arranged to receive the communication signals from the fifth capacitive plate and to provide the communication signals to the input of the receiver,

a third dielectric layer defining second breakdown voltages of the second capacitive structure by providing an electrical and physical separation between the fifth capacitive plate and each of the fourth and sixth capacitive plates, the physical separation having a second distance, and

a fourth dielectric layer providing an electrical and physical separation between the second substrate and the fifth capacitive plate to provide substantially the same breakdown voltages as the second breakdown voltages.

6. The device of claim 5, wherein the first and second substrates are respective silicon-on-insulator (SOI) substrates.

7. The device of claim 6, wherein each of the SOI substrates includes a respective and corresponding handle wafer, silicon layer and buried oxide layer, the buried oxide layer providing isolation between the handle wafer the silicon layer.

8. The device of claim 7, wherein the handle wafer of the first substrate is tied to a ground voltage of the first voltage domain, the handle wafer of the second substrate is tied to a ground voltage of the second voltage domain, and wherein at least a portion of each of the silicon layers for the first and second SOI substrates are floating.

9. The device of claim 7, wherein the communication signals are differential signals and wherein the isolation circuit includes additional capacitive structures for providing capacitive isolation of the differential signals.

10. The device of claim 5, wherein the first and second distances are set such that breakdown voltages are substantially the same between each of the second capacitive plate and the first substrate, the second capacitive plate and the first capacitive plate, the fifth capacitive plate and the second substrate, and the fifth capacitive plate and the sixth capacitive plate.

11. The device of claim 5, wherein each of the first and second capacitive structures are configured to have a lateral breakdown voltage between the first and third capacitive plates and the fourth and six capacitive plates, respectively, that is at least twice a vertical breakdown voltage between the first and second capacitive plates and the fourth and fifth capacitive plates, respectively.

12. The device of claim 7, wherein the first and second buried oxide layers are at least 1 micrometer thick.

13. The device of claim 7, wherein each of the SOI substrates includes a respective and corresponding handle wafer, a silicon layer and a buried oxide layer providing isolation between the handle wafer and the silicon layer, and wherein each of the first and second capacitive structures includes a respective oxide ring surrounding and providing electrical isolation for a portion of the respective silicon layer that is floating.

14. The device of claim 13, wherein each respective oxide ring is provided using a trench isolation structure that surrounds the portion of the respective silicon layer and that has a lateral voltage breakdown substantially the same as a vertical breakdown voltage of the respective buried oxide layer.

15. The device of claim 13, wherein the transmitter is configured and arranged to generate the communication signals having a voltage of about 10 V or less relative to a first ground potential of the first voltage domain and the receiver is configured and arranged to receive the communication signals having a voltage of about 10 V or less relative to a second ground potential of the second voltage domain.

16. A method comprising:

transmitting communication signals from a transmitter circuit located on a first substrate that is in a first voltage domain;

providing capacitive isolation for the communication signals between the first voltage domain and a second voltage domain by communicating the transmitted communication signals through an isolation circuit by

capacitively coupling the communication signals from the first voltage domain to an unreferenced domain using a first capacitive structure located on the first substrate and including

a first capacitive plate configured and arranged to receive the communication signals from the transmitter circuit and in the first voltage domain,

a second capacitive plate that is configured and arranged to receive the communication signals from the first capacitive plate at a first floating node of the isolation circuit,

a third capacitive plate that is configured and arranged to receive the communication signals from the second capacitive plate at a second floating node of the isolation circuit,

a first dielectric layer configured and arranged to provide first breakdown voltages of the first capacitive structure by providing an electrical and physical separation between the second capacitive plate and each of the first and third capacitive plates, the physical separation having a first distance, and

a second dielectric layer providing an electrical and physical separation between the first substrate and the second capacitive plate to provide substantially the same breakdown voltages as the first breakdown voltages;

capacitively coupling using the communication signals from the unreferenced voltage domain to the second voltage domain using a second capacitive structure located on the second substrate in the second voltage domain and including

a second capacitive structure located on the second substrate and including,

a fourth capacitive plate configured and arranged to receive the communication signals at a third floating node of the isolation circuit from a conductor that provides a current path between the third and fourth capacitive plates,

a fifth capacitive plate configured and arranged to receive the communication signals from the fourth capacitive plate at a fourth floating node of the isolation circuit,

a sixth capacitive plate configured and arranged to receive the communication signals from the fifth capacitive plate and to provide the communication signals to the input of the receiver,

a third dielectric layer defining second breakdown voltages of the second capacitive structure by providing an electrical and physical separation between the fifth capacitive plate and each of the fourth and sixth capacitive plates, the physical separation having a second distance, and

a fourth dielectric layer providing an electrical and physical separation between the second substrate and the fifth capacitive plate to provide substantially the same breakdown voltages as the second breakdown voltages; and

receiving the communication signals from the second capacitive structure at an input of a receiver circuit that is in the second voltage domain.

17. The method of claim 16, wherein the first and second substrates are respective silicon-on-insulator (SOI) substrates.

18. The method of claim 17, wherein each of the SOI substrates includes a respective and corresponding handle wafer, a silicon layer and a buried oxide layer providing isolation between the handle wafer the silicon layer.

19. The method of claim 18, further comprising:

setting the handle wafer of the first substrate to a first ground voltage of the first voltage domain, and

setting the handle wafer of the second substrate to a second ground voltage of the second voltage domain,

isolating at least a portion of each of the silicon layer of the first substrate from the first ground voltage, and

isolating at least a portion of each of the silicon layer of the first substrate from the second ground voltage.

20. The method of claim 17, wherein the first and second distances are set such that breakdown from the second plate towards the first substrate is substantially the same as that from the second plate towards the first plate, and such that breakdown voltages from the fifth plate towards the second substrate is substantially the same as that from the fifth plate towards the sixth plate.

21. The method of claim 16, wherein each of the first and second capacitive structures are configured to have a lateral breakdown voltage between the first and third plates and the fourth and six plates, respectively, that is at least twice a vertical breakdown voltage between the first and second plates and the fourth and fifth plates, respectively.

22. The method of claim 18, wherein the first and second buried oxide layers are at least 1 micrometer thick.

23. The method of claim 17, wherein each of the SOI substrates includes a respective and corresponding handle wafer, a silicon layer and a buried oxide layer providing isolation between the handle wafer the silicon layer, the method further including, for each of the first and second capacitive structures, electrically isolating a portion of the respective silicon layer using an oxide ring surrounding the portion in the silicon layer.