Methods and apparatus for processing serialized video data for display

• US 9,007,357 B2
• Filed: 07/31/2007
• Issued: 04/14/2015
• Est. Priority Date: 01/03/2007
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Dae-Jin, Kim, Jong-Seon, Lee, Jae-Youl, Kim, Chang-Min
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): BARTELS, CHRISTOPHER A.
• Application Number:
  US11/831,151
• Publication Number:
  US 20080158424A1
• Time in Patent Office: 2,814 Days
• Field of Search: None
• US Class Current: 345/213
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 5/18 Timing circuits for raster scan displays specially adapted for television H04N ; synchronisation between the display unit and other display units, videodisc player G09G5/12

Abstract

A method of deserializing signals output from a master can include generating an indication signal based on occurrence of a first signal pattern input via a data line during a first period and occurrence of a second signal pattern input via a clock line during the first period and enabling a deserializer in response to the indication signal and deserializing serialized video data input via the data line during a second period following the first period, in response to a clock signal input via the clock line during the second period. Related circuits are also disclosed.

Claims

1. A method of deserializing signals output from a master, the method comprising:

generating an indication signal by a column driver based on occurrence of a first signal pattern input via a data line during a first period and occurrence of a second signal pattern input via a clock line during the first period, wherein the indication signal indicates a time at which valid video data starts in a packet; and

enabling a deserializer in response to the indication signal and deserializing serialized video data input via the data line during a second period following the first period, in response to a clock signal input via the clock line during the second period,

wherein the serialized video data and the first signal pattern are received via the data line by a slave comprising the column driver and coupled to the master,

wherein the indication signal is disabled during the second period, and

wherein generating the indication signal comprises generating the indication signal by the column driver before the indication signal is disabled and before deserializing the serialized video data.

2. The method of claim 1, wherein the first signal pattern includes N oscillations between a first logic state and a second logic state during the first period and the second signal pattern maintains the first logic state during the first period where N is a natural number.

3. The method of claim 1, wherein the first signal pattern comprises information used to indicate subsequent timing for subsequent de-serialization of serialized video data during the second period.

4. The method of claim 3, wherein the information included in the first signal pattern is absent from a video panel on which the de-serialized video data is displayed.

5. The method of claim 1, wherein:

the packet includes the first signal pattern and the serialized video data;

the slave receives differential data signals from the master and detects the packet that includes the first signal pattern and the serialized video data in response to receiving the differential data signals;

the clock signal includes the second signal pattern; and

the slave receives differential clock signals from the master and detects the clock signal that includes the second signal pattern in response to receiving the differential clock signals.

6. A data processing apparatus comprising:

an indication signal detector configured to detect an indication signal based on occurrence of a first signal pattern input via a data line during a first period and occurrence of a second signal pattern input via a clock line during the first period, wherein the indication signal is generated by a column driver and indicates a time at which valid video data starts in a packet; and

a deserializer, coupled to the indication signal detector, configured to be enabled responsive to the indication signal and to deserialize serialized video data input via the data line, in response to a clock signal input via the clock line during a second period after the first period,

wherein the serialized video data and the first signal pattern are input via the data line,

wherein the indication signal is disabled during the second period, and

wherein the indication signal is generated by the column driver before the indication signal is disabled and before the deserializer deserializes the serialized video data.

7. The data processing apparatus of claim 6, wherein the first signal pattern includes N oscillations between a first logic state and a second logic state during the first period and the second signal pattern maintains the first logic state during the first period where N is a natural number.

8. The data processing apparatus of claim 6, wherein the indication signal detector is reset responsive to N oscillations of a second signal, providing the second signal pattern over time, between a first logic state and a second logic state where N is a natural number.

9. The data processing apparatus of claim 6, wherein the indication signal detector comprises:

a logic circuit configured to receive the first signal pattern and the serialized video data via the data line and the second signal pattern and the clock signal via the clock line, to perform a logic operation thereon and to output a signal responsive thereto;

a first flip-flop comprising an input terminal for receiving an inverted first output signal, a clock terminal for receiving the signal output from the logic circuit, an output terminal for outputting a first output signal, and a reset terminal for receiving the clock signal; and

a second flip-flop, coupled to the first flip-flop, comprising an input terminal for receiving an inverted indication signal, a clock terminal for receiving the inverted first output signal, an output terminal for outputting the indication signal, and a reset terminal for receiving the clock signal.

10. The data processing apparatus of claim 6, further comprising a display panel configured to display an image based on video data and the clock signal, which are output from the deserializer.

11. A data processing apparatus comprising:

a master configured to output a first signal pattern via a data line and a second signal pattern via a clock line during a first period and to serialize parallel video data and output serialized video data via the data line and a clock signal via the clock line during a second period following the first period; and

a slave, coupled to the master, the slave comprising a column driver configured to generate an indication signal based on the first signal pattern and the second signal pattern during the first period and to deserialize the serialized video data in response to the indication signal and the clock signal during the second period,

wherein the indication signal indicates a time at which valid video data starts in a packet,

wherein the slave is configured to receive the serialized video data and the first signal pattern via the data line,

wherein the indication signal is disabled during the second period,

wherein the column driver is configured to generate the indication signal before the indication signal is disabled and before deserializing the serialized video data.

12. The data processing apparatus of claim 11, wherein the slave comprises:

an indication signal detector configured to detect the indication signal based on the first signal pattern and the second signal pattern during the first period; and

a deserializer configured to be enabled in response to the indication signal and to deserialize the serialized video data in response to the clock signal.

13. The data processing apparatus of claim 12, wherein the first signal pattern includes N oscillations between a first logic state and a second logic state during the first period and the second signal pattern maintains the first logic state during the first period where N is a natural number.

14. The data processing apparatus of claim 12, wherein the indication signal detector is reset when the second signal pattern includes N oscillations between a first logic state and a second logic state where N is a natural number.

15. The data processing apparatus of claim 12, wherein the indication signal detector comprises:

a logic circuit configured to receive the first signal pattern and the serialized video data via the data line and the second signal pattern and the clock signal via the clock line, to perform a logic operation on them, and to output a signal according to a result of the logic operation;

a first flip-flop comprising an input terminal for receiving an inverted first output signal, a clock terminal for receiving the signal output from the logic circuit, an output terminal for outputting a first output signal, and a reset terminal for receiving the clock signal; and

a second flip-flop comprising an input terminal for receiving an inverted indication signal, a clock terminal for receiving the inverted first output signal, an output terminal for outputting the indication signal, and a reset terminal for receiving the clock signal.

16. The data processing apparatus of claim 12, further comprising a display panel configured to display an image based on video data and the clock signal, which are output from the deserializer.

17. A data processing method comprising:

outputting a first signal pattern via a data line and a second signal pattern via a clock line during a first period, and serializing parallel video data and outputting serialized video data via the data line and a clock signal via the clock line during a second period; and

generating an indication signal by a column driver based on the first signal pattern and the second signal pattern during the first period, and enabling a deserializer in response to the indication signal and deserializing the serialized video data in response to the clock signal during the second period,

wherein the indication signal indicates a time at which valid video data starts in a packet,

wherein the serialized video data and the first signal pattern are input via the data line,

wherein the indication signal is disabled during the second period, and

wherein generating the indication signal comprises generating the indication signal by the column driver before the indication signal is disabled and before deserializing the serialized video data.

18. The data processing method of claim 17, wherein the first signal pattern includes N oscillations between a first logic state and a second logic state during the first period and the second signal pattern maintains the first logic state during the first period where N is a natural number.

19. The data processing method of claim 17, wherein the packet includes video data that will be displayed on a video panel.