Mapped FIFO buffering
First Claim
1. A network interface device for connection between a network and a data processing system, the network interface device comprising:
- an I/O interface for connection to a data processing system;
a set of physical data ports for connection to a network;
a unified memory comprising a plurality of buffers for buffering data packets directed to the data processing system before the data packets are provided to the I/O interface;
a plurality of ingress ports operable to receive data packets for buffering at the unified memory, a first subset of the plurality of ingress ports being configured to receive data packets on a transmit path from said data processing system, and a second subset of the plurality of ingress ports being configured to receive data packets on a receive path from said set of physical data ports;
a memory manager configured to store representations of a plurality of virtual queues held in the unified memory, each virtual queue being a linked logical sequence of buffers of the unified memory; and
an ingress interface configured to service the ingress ports in a predetermined order and write data packets received at the ingress ports to buffers of the unified memory selected by the memory manager;
wherein the memory manager is arranged to select buffers of the unified memory so as to cause the ingress interface to populate the plurality of virtual queues with data packets, and the ingress interface is arranged to contiguously write data packets into the linked logical sequence of buffers representing each virtual queue and the ingress interface is configured to delineate data packets by writing an end-of-packet control word such that each buffer is able to store a plurality of data packets and such that a single data packet is able to span a plurality of buffers.
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Accused Products
Abstract
A network interface device for connection between a network and a data processing system, the network interface device comprising: an I/O interface for connection to a data processing system; a set of physical data ports for connection to a network; a unified memory comprising a plurality of buffers; a plurality of ingress ports operable to receive data packets for buffering at the unified memory, a first subset of the plurality of ingress ports being configured to receive data packets on a transmit path from said I/O interface, and a second subset of the plurality of ingress ports being configured to receive data packets on a receive path from said set of physical data ports; a memory manager configured to store representations of a plurality of virtual queues held in the unified memory, each virtual queue being a linked logical sequence of buffers of the unified memory; and an ingress interface configured to service the ingress ports in a predetermined order and write data packets received at the ingress ports to buffers of the unified memory selected by the memory manager; wherein the memory manager is arranged to select buffers of the unified memory so as to cause the ingress interface to populate the plurality of virtual queues with data packets, and the ingress interface is arranged to contiguously write data packets into the linked logical sequence of buffers representing each virtual queue.
162 Citations
34 Claims
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1. A network interface device for connection between a network and a data processing system, the network interface device comprising:
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an I/O interface for connection to a data processing system; a set of physical data ports for connection to a network; a unified memory comprising a plurality of buffers for buffering data packets directed to the data processing system before the data packets are provided to the I/O interface; a plurality of ingress ports operable to receive data packets for buffering at the unified memory, a first subset of the plurality of ingress ports being configured to receive data packets on a transmit path from said data processing system, and a second subset of the plurality of ingress ports being configured to receive data packets on a receive path from said set of physical data ports; a memory manager configured to store representations of a plurality of virtual queues held in the unified memory, each virtual queue being a linked logical sequence of buffers of the unified memory; and an ingress interface configured to service the ingress ports in a predetermined order and write data packets received at the ingress ports to buffers of the unified memory selected by the memory manager; wherein the memory manager is arranged to select buffers of the unified memory so as to cause the ingress interface to populate the plurality of virtual queues with data packets, and the ingress interface is arranged to contiguously write data packets into the linked logical sequence of buffers representing each virtual queue and the ingress interface is configured to delineate data packets by writing an end-of-packet control word such that each buffer is able to store a plurality of data packets and such that a single data packet is able to span a plurality of buffers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A network interface device for connection between a network and a data processing system, the network interface device comprising:
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an I/O interface for connection to a data processing system; a set of physical data ports for connection to a network; a unified memory comprising a plurality of buffers for buffering data packets directed to the data processing system before the data packets are provided to a the I/O interface; a plurality of ingress ports operable to receive data packets for buffering at the unified memory, a first subset of the plurality of ingress ports being configured to receive data packets on a transmit path from said I/O interface, and a second subset of the plurality of ingress ports being configured to receive data packets on a receive path from said set of physical data ports; a memory manager configured to store representations of a plurality of virtual queues held in the unified memory, each virtual queue being a linked logical sequence of buffers of the unified memory; and an ingress interface configured to service the ingress ports in a predetermined order and write data packets received at the ingress ports to buffers of the unified memory selected by the memory manager; wherein the memory manager is arranged to select buffers of the unified memory so as to cause the ingress interface to populate the plurality of virtual queues with data packets, and the ingress interface is arranged to contiguously write data packets into the linked logical sequence of buffers representing each virtual queue and the memory manager is configured to allocate buffers not linked to a virtual queue to one or more free buffer pools and to, on a virtual queue becoming full, append a buffer selected from one of the one or more free buffer pools to that virtual queue. - View Dependent Claims (27, 28, 29, 30, 31)
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32. A network interface device for connection between a network and a data processing system, the network interface device comprising:
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an I/O interface for connection to a data processing system; a set of physical data ports for connection to a network; a unified memory comprising a plurality of buffers for buffering data packets directed to the data processing system before the data packets are provided to a the I/O interface; a plurality of ingress ports operable to receive data packets for buffering at the unified memory, a first subset of the plurality of ingress ports being configured to receive data packets on a transmit path from said I/O interface, and a second subset of the plurality of ingress ports being configured to receive data packets on a receive path from said set of physical data ports; a memory manager configured to store representations of a plurality of virtual queues held in the unified memory, each virtual queue being a linked logical sequence of buffers of the unified memory; and an ingress interface configured to service the ingress ports in a predetermined order and write data packets received at the ingress ports to buffers of the unified memory selected by the memory manager; wherein the memory manager is arranged to select buffers of the unified memory so as to cause the ingress interface to populate the plurality of virtual queues with data packets, and the ingress interface is arranged to contiguously write data packets into the linked logical sequence of buffers representing each virtual queue and the memory manager is configured to maintain for each virtual queue active buffer parameters representing an active buffer to which packet data received at an associated ingress port is to be written and a write offset in the active buffer at which writing is to commence. - View Dependent Claims (33)
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34. A method for buffering data packets at a network interface device, the network interface device having an I/O interface for connection to a data processing system, a set of one or more physical data ports for connection to a network, a unified memory comprising a plurality of buffers and a plurality of ingress ports operable to receive data packets for buffering at the unified memory, the plurality of ingress ports including a first subset of ingress ports configured to receive data packets on a transmit path from said data processing system and a second subset of ingress ports configured to receive data packets on a receive path from said set of physical data ports, the method comprising:
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buffering data packets directed to the data processing system before the data packets are provided to the I/O interface by; servicing the ingress ports in a predetermined order so as to receive data packets from the ingress ports; selecting for each data packet received at an ingress port a buffer of a virtual queue held in the unified memory, each virtual queue being a linked logical sequence of buffers of the unified memory; and writing data packets received at the ingress ports to the selected buffers of the unified memory such that the linked logical sequence of buffers representing each virtual queue is contiguously populated with data packets; servicing the virtual queues in sequence according to a specified service order so as to provide data packets de-queued from the virtual queues at an egress port; and directing data packets received at the egress port to one or more of;
a receive engine for delivery over the I/O interface;
a virtualised interface of the network interface device, and the transmit path for delivery over a physical data port of the NIC;wherein the service order is maintained in dependence on one or both of;
the number of buffers in each of the virtual queues, and a priority level of each of the virtual queues.
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Specification