Timing channel circuitry for creating pulses in an implantable stimulator device
First Claim
1. An implantable stimulator device, comprising:
- a memory for storing pulse parameters defining a plurality of pulse phases for a periodic pulse, wherein the memory is addressable via an address bus to provide via a data bus the pulse parameters to stimulation circuitry for forming the pulse phases at electrodes for stimulating a patient'"'"'s tissue,wherein the pulse parameters for at least one of the pulse phases are stored in a plurality of addresses in the memory,wherein a first address in the memory for the pulse parameters for each of the plurality of pulse phases comprises a pre-defined data structure.
1 Assignment
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Accused Products
Abstract
Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.
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Citations
32 Claims
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1. An implantable stimulator device, comprising:
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a memory for storing pulse parameters defining a plurality of pulse phases for a periodic pulse, wherein the memory is addressable via an address bus to provide via a data bus the pulse parameters to stimulation circuitry for forming the pulse phases at electrodes for stimulating a patient'"'"'s tissue, wherein the pulse parameters for at least one of the pulse phases are stored in a plurality of addresses in the memory, wherein a first address in the memory for the pulse parameters for each of the plurality of pulse phases comprises a pre-defined data structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An implantable stimulator device, comprising:
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a memory for storing pulse parameters defining a plurality of pulse phases for a periodic pulse, wherein the memory is addressable via an address bus to provide via a data bus the pulse parameters to stimulation circuitry for forming the pulse phases at electrodes for stimulating a patient'"'"'s tissue, wherein the pulse parameters for at least one of the pulse phases are stored in a plurality of addresses in the memory, wherein the pulse parameters for the plurality of pulse phases do not comprise the same number of addresses in the memory. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. An implantable stimulator device, comprising:
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a memory for storing pulse parameters defining a plurality of pulse phases for a periodic pulse, wherein the memory is addressable via an address bus to provide via a data bus the pulse parameters to stimulation circuitry for forming the pulse phases at electrodes for stimulating a patient'"'"'s tissue, wherein the pulse parameters for at least one of the pulse phases are stored in a plurality of addresses in the memory, wherein the pulse parameters comprise amplitude data and active electrode and electrode polarity data for at least some of the plurality of pulse phases. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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Specification