Method and apparatus for processing received network packets on a network interface for a computer

• US 9,009,223 B2
• Filed: 05/21/2013
• Issued: 04/14/2015
• Est. Priority Date: 10/14/1997
• Status: Expired due to Fees

• Current Assignee: Alacritech, Inc.
• Original Assignee: Alacritech, Inc.
• Inventors: Boucher, Laurence B., Blightman, Stephen E. J., Craft, Peter K., Higgen, David A., Philbrick, Clive M., Starr, Daryl D.
• Primary Examiner(s): Nguyen, Tammy
• Application Number:
  US13/899,299
• Publication Number:
  US 20130326083A1
• Time in Patent Office: 693 Days
• Field of Search: 709/203, 714/807, 717/144
• US Class Current: 709/203
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: H04L 45/66 Layer 2 routing, e.g. in Ethernet based MAN's
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/193 at the transport layer, e.g. TCP related
• CPC Class Codes: H04L 47/36 by determining packet size, e.g. maximum transfer unit [MTU]
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/6225 Fixed service order, e.g. Round Robin
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9021 Plurality of buffers per packet
• CPC Class Codes: H04L 49/9042 Separate storage for different parts of the packet, e.g. header and payload
• CPC Class Codes: H04L 49/9052 with buffers of different sizes
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9068 in the network interface card
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 61/00 Network arrangements, protocols or services for addressing or naming
• CPC Class Codes: H04L 61/10 : of different types
• CPC Class Codes: H04L 67/10 : in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46
• CPC Class Codes: H04L 67/34 : involving the movement of software or configuration parameters network booting or remote initial program loading [RIPL] G06F9/4416
• CPC Class Codes: H04L 67/62 : Establishing a time schedule for servicing the requests
• CPC Class Codes: H04L 67/63 : Routing a service request depending on the request content or context
• CPC Class Codes: H04L 69/08 : Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 69/12 : Protocol engines
• CPC Class Codes: H04L 69/16 : Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 : Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/162 : involving adaptations of sockets based mechanisms secure socket layer H04L63/168
• CPC Class Codes: H04L 69/163 : In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/166 : IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/22 : Parsing or analysis of headers
• CPC Class Codes: H04L 69/32 : Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 9/40 : Network security protocols

Abstract

An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offloading time-intensive processing tasks from the host CPU. The host retains a fallback processing capability for messages that do not fit fast-path criteria, with the device providing assistance such as validation even for slow-path messages, and messages being selected for either fast-path or slow-path processing. A context for a connection is defined that allows the device to move data, free of headers, directly to or from a destination or source in the host. The context can be passed back to the host for message processing by the host. The device contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors devoted to transmit, receive and utility processing, providing full duplex communication for four Fast Ethernet nodes.

Claims

1. A method of network communication for a network interface that is coupled to a computer by an input/output (I/O) bus, the method comprising:

running, on the computer, a protocol processing stack including an Internet Protocol (IP) layer and a Transmission Control Protocol (TCP) layer, with an upper layer running above the TCP layer;

maintaining, on the network interface, a TCP control block (TCB);

receiving, by the network interface, a network packet having an IP header, a TCP header, and an upper layer header;

processing the packet by the network interface, including parsing the IP header and TCP header to associate the packet with the TCB;

updating, by the network interface, the TCB to reflect receiving the packet; and

parsing, by the network interface, the upper layer header to determine a length of data being received in a plurality of network packets that correspond to the TCB and include the network packet.

4. The method of claim 1, including sending the length that was determined by the network interface from the network interface to the computer.

5. The method of claim 1, including sending the data from the network interface to a buffer of the computer.

6. The method of claim 5, including allocating the buffer by a layer above the TCP layer.

7. The method of claim 1, including sending the data from the network interface to the computer without sending any IP headers or TCP headers of the plurality of network packets from the network interface to the computer.

8. The method of claim 1, including allocating a buffer of the computer based upon the length that was determined by the network interface.

9. The method of claim 1, including using the length that was determined by the network interface to determine when all of the data has been received by the network interface.

10. The method of claim 1, including using the length that was determined by the network interface to decide whether to send the data from the network interface to the computer immediately or to wait to send the data until after the network interface has received from the computer a location in a memory of the computer in which to store the data.

2. A system for communication over a network, the system comprising:

a computer running a protocol processing stack including an Internet Protocol (IP) layer and a Transmission Control Protocol (TCP) layer, with an upper layer running above the TCP layer; and

a network interface that is coupled to the computer by an input/output (I/O) bus, the network interface including a memory storing a TCP control block (TCB) and a mechanism adapted to parse IP and TCP headers of received network packets to determine whether the received network packets correspond to the TCB, the mechanism adapted to parse an upper layer header of one of the received network packets to determine a length of data being received in the plurality of the packets that correspond to the TCB.

11. The system of claim 2, wherein the network interface includes a processor that accesses the TCB.

12. The system of claim 2, wherein the mechanism that is adapted to parse the headers of the received network packets includes specialized network processing hardware.

13. The system of claim 2, wherein the network interface includes a processor that accesses the TCB.

14. The system of claim 2, wherein the computer includes a memory buffer that is allocated for storing the data.

15. The system of claim 2, wherein the network interface includes a direct memory access (DMA) engine that is adapted to store the data in a memory buffer of the computer.

3. A network interface that is coupled to a computer by an input/output (I/O) bus, the network interface comprising:

hardware adapted to parse Internet Protocol (IP) headers and Transmission Control Protocol (TCP) headers of received network packets to determine whether the received network packets correspond to a TCP control block (TCB) being stored on the network interface, and hardware adapted to parse an upper layer header of one of the received network packets to determine a length of data being received in a plurality of the packets that correspond to the TCB.

16. The network interface of claim 3, including a processor that accesses the TCB.

17. The network interface of claim 3, including a direct memory access (DMA) engine that is adapted to store the data in a memory buffer of the computer.