High speed cryptographic combining system, and method for programmable logic devices

• US 9,009,495 B2
• Filed: 06/28/2013
• Issued: 04/14/2015
• Est. Priority Date: 06/28/2013
• Status: Active Grant

• Current Assignee: Envieta, LLC
• Original Assignee: Envieta, LLC
• Inventors: Daniel, Arthur Mark, Petro, John, Millhollon, Timothy Mark
• Primary Examiner(s): Lim, Krisna
• Application Number:
  US13/931,585
• Publication Number:
  US 20150006913A1
• Time in Patent Office: 655 Days
• Field of Search: 713/193
• US Class Current: 713/193
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 21/755 with measures against power attack
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H04L 9/00 Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
• CPC Class Codes: H04L 9/0816 Key establishment, i.e. cryptographic processes or cryptographic protocols whereby a shared secret becomes available to two or more parties, for subsequent use

Abstract

A system, apparatus, method, and/or computer program product is disclosed for decreasing side channel signal leakage and increasing speed of cryptographic combining operations. An exemplary method may be incorporated, in an exemplary embodiment, in an exemplary programmable logic device (PLD) such as, e.g., but not limited to, a field programmable gate array (FPGA) implementation of at least one cryptographic combining process, or may include an application specific integrated circuit (ASIC) design where cryptographic combining with minimal side channel signal leakage and high speed are provided.

Claims

1. A method comprising:

receiving, by at least one cryptographic combiner device, at least one large bit length input value; and

transforming, by said at least one cryptographic combiner device, said at least one large bit length input value into at least one output value,

wherein said transforming comprises

transforming, by said at least one cryptographic combiner device, said at least one large bit length input value into said at least one output value within a single clock cycle.

2. The method according to claim 1, wherein said at least one cryptographic combiner device comprises at least a portion of:

at least one programmable logic device (PLD).

3. The method according to claim 2, wherein said at least one PLD comprises at least one of:

at least one field programmable gate array (FPGA);

at least one application specific integrated circuit (ASIC);

at least one programmable logic array (PLA);

at least one programmable read only memory (PROM);

at least one erasable programmable read only memory (EPROM);

at least one electrically erasable programmable read only memory (EEPROM);

at least one programmable array logic (PAL);

at least one generic array logic (GAL);

at least one programmable electrically erasable logic (PEEL);

at least one semiconductor intellectual property core (IP core);

or

at least one complex programmable logic device (CPLD).

4. The method according to claim 1, wherein said transforming is performed on an entirety of said large bit length input value.

5. The method according to claim 1, wherein said cryptographic combiner device comprises:

at least one bank of at least one look-up-table (LUT), each said at least one LUT receiving as input a plurality of single bit input values, and providing as output at least one output bit,

wherein when said cryptographic combiner device comprises a plurality of banks of said at least one LUT, the at least one output bit from a first of said plurality of banks is wired to feed into the input of said at least one LUT of a second of said plurality of banks, and

wherein a total number of banks of said at least one LUTs is any number so long as said large bit length input reaches an output of the last bank of said plurality of banks, to produce said at least one output value, within a single clock cycle.

6. The method according to claim 5, wherein said performing comprises:

performing said transforming on said plurality of banks of said at least one look-up-table (LUT), wherein said at least one LUT comprises at least one of;

a small LUT;

a programmable LUT;

or

an n-bit input to x-bit output LUT.

7. The method according to claim 6, wherein said at least one LUT comprises an n-bit input to x-bit output LUT, and wherein said n-bit input LUT comprises an at least six (6)-bit input LUT, and said x-bit output LUT comprises an at least one (1)-bit output LUT.

8. The method according to claim 6, wherein said at least one LUT comprises an n-bit input to x-bit output LUT, and, wherein said plurality of banks comprises a plurality m banks, where m is greater than 1, and wherein each of said m banks comprises a plurality Tj LUTs of said at least one LUT for each bank j=1, 2, . . . , m, wherein for each of said plurality m banks of said plurality Tj LUTs accepts a product Tj*n input bits and produces as output a product Tj*x output bits for each bank j=1, 2, . . . , m.

9. The method according to claim 8, wherein each of said m banks is adapted to operate in parallel and with sufficient efficiency comprising at least one of:

that computing said at least one output value,

processing to obtain said at least one output value, or

feeding through all said m banks to obtain said at least one output value within said single clock cycle.

10. The method according to claim 8, wherein said at least one LUT comprises said n-bit input to x-bit output LUT, wherein 1<

=j<

m, and wherein at least one output from a given bank j, is coupled to at least one of T(j+1)*n inputs to next bank j+1.

11. The method according to claim 10, wherein said coupling comprises programmably wiring said at least one output from said given bank j to feed to said at least one of said T(j+1)*n inputs of said next bank j+1.

12. The method according to claim 8, wherein said at least one LUT comprises said n-bit input to x-bit output LUT, and wherein signals propagate through all said m plurality banks within said single clock cycle.

13. The method according to claim 10, wherein said coupling comprises at least one inter-bank coupling.

14. The method according to claim 13, further comprising:

altering said at least one interbank coupling or at least one parameter of said at least one LUT to achieve a plurality of cryptographic functions.

15. The method according to claim 14, further comprising at least one of:

wherein said altering comprises programmably altering said at least one interbank coupling or said at least one parameter of said at least one LUT;

wherein said at least one interbank coupling comprises at least one changeable coupling;

wherein said altering comprises dynamically altering said at least one interbank coupling or said at least one parameter of said at least one LUT;

wherein said altering comprises altering dynamically during use;

or

wherein said altering comprises altering dynamically over time, during use.

16. The method according to claim 1, wherein said transforming comprises:

combining at least one fixed secret value with at least one time varying input value comprising transforming said at least one fixed secret value into at least one second time varying secret value.

17. The method according to claim 16, wherein said transforming comprises:

using said at least one second time varying secret value in at least one subsequent cryptographic processing wherein a secret value is required.

18. The method according to claim 2, wherein said cryptographic combiner device comprises:

said portion of said at least one PLD, wherein said receiving said large bit length input value and said transforming said large bit length input value into said output value on said PLD comprises;

performing a full transformation on an entire input within said single PLD clock cycle by using at least one programmable LUT in fabric of said PLD.

19. The method according to claim 1, wherein said input value constitutes at least one fixed secret value and at least one time varying quantity so as to obscure said at least one fixed secret value and minimizing side channel information leakage about said at least one fixed secret.

20. The method according to claim 3, wherein said input value constitutes at least one secret and at least one time varying quantity, wherein when combined obscures said at least one secret, and minimizes side channel information leakage as could be used to detect said at least one secret.

21. The method according to claim 17, wherein said PLD comprises at least one of:

at least one application specific integrated circuit (ASIC);

at least one programmable logic array (PLA);

at least one programmable array logic (PAL);

at least one programmable read only memory (PROM);

at least one erasable programmable read only memory (EPROM);

at least one electrically erasable programmable read only memory (EEPROM);

at least one generic array logic (GAL);

at least one programmable electrically erasable logic (PEEL);

at least one semiconductor intellectual property core (IP core);

at least one intellectual property core (IP core);

at least one photonic processor;

or

at least one complex programmable logic device (CPLD).

22. The method according to claim 16, wherein said time varying secret value is used as a key for at least one of:

an encryption function, or a keyed message authentication code (MAC) function.

23. The method according to claim 16, wherein said time varying secret value comprises the key to the advanced encryption standard (AES).

24. The method according to claim 16, wherein said time varying secret value is used as a pseudo-random bit stream for a cryptographic application.

25. The method according to claim 24, wherein said time varying secret value is used as said pseudo-random bit stream for said cryptographic application, to perform an XOR operation over an input data stream as a stream cipher.

26. A system comprising:

a cryptographic device comprising;

at least one cryptographic combiner adapted to receive at least one large bit length input value; and

wherein said at least one cryptographic combiner is adapted to transform the at least one large bit length input value into at least one output value, and

wherein said at least one cryptographic combiner is adapted to transform the at least one large bit length input value into said at least one output value within a single clock cycle.

27. The system according to claim 26, wherein said cryptographic device further comprises:

at least one key cryptographic function comprising at least one input coupled to at least one output of said at least one cryptographic combiner.

28. The system according to claim 27, wherein said at least one key cryptographic function comprises an advanced encryption standard (AES) key cryptographic function.

29. The system according to claim 26, wherein the at least one large bit length input value comprises at least one output of at least one processor.

30. The system according to claim 26, wherein said at least one cryptographic combiner comprises at least a portion of:

at least one programmable logic device (PLD).

31. The system according to claim 30, wherein said at least one PLD comprises at least one of:

at least one field programmable gate array (FPGA);

at least one application specific integrated circuit (ASIC);

at least one programmable logic array (PLA);

at least one programmable read only memory (PROM);

at least one erasable programmable read only memory (EPROM);

at least one electrically erasable programmable read only memory (EEPROM);

at least one programmable array logic (PAL);

at least one generic array logic (GAL);

at least one programmable electrically erasable logic (PEEL);

at least one semiconductor intellectual property core (IP core);

or

at least one complex programmable logic device (CPLD).