Power state synchronization in a multi-core processor
First Claim
1. A multi-core processor comprising:
- a plurality of physical processing cores;
inter-core state discovery microcode in each core enabling the core to participate in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, sent to or received from other cores;
wherein the inter-core state discovery microcode includes synchronization logic, provided to each core, synchronized instances of which are operable to be invoked on multiple cores for purposes of an inter-core state discovery process;
wherein each native instance is operable both to invoke new instances of the synchronization logic on other cores, and to respond to any prior instance of the synchronization logic on another core that invoked the native instance;
wherein the hierarchical coordination system groups cores into a plurality of domain levels, including at least;
a primary-level domain of highest rank that includes all of the cores; and
two or more secondary-level domains of equal next rank, immediately below the highest rank, that are constituents of and nested within the primary-level domain, each secondary-level group comprising respectively exclusive subgroups of the cores;
for each multi-core domain level, a single core is designated as a master of that domain;
each multi-core domain other than the lowest-level multi-core domains defines a kinship group consisting of master cores of constituent domains of the immediately next lower rank;
each lowest-level multi-core domain defines a kinship group consisting of all of its cores;
each core belongs to at least one kinship group; and
each native instance of the synchronization logic is restricted from invoking new instances of the synchronization logic to cores not belonging to a native core kinship group.
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Abstract
A multi-core processor includes microcode distributed in each core enabling each core to participate in a de-centralized inter-core state discovery process. In a related microcode-implemented method, states of a multi-core processor are discovered by at least two cores participating in a de-centralized inter-core state discovery process. The inter-core state discovery process is carried out through a combination of microcode executing on each participating core and signals exchanged between the cores through sideband non-system-bus communication wires. The discovery process is unmediated by any centralized non-core logic. Applicable discoverable states include target and composite power states, whether and how many cores are enabled, the availability and distribution of various resources, and hierarchical structures and coordination systems for the cores. The inter-core state discovery process may be carried out in accordance with various hierarchical coordination systems involving chained inter-core communications.
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Citations
16 Claims
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1. A multi-core processor comprising:
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a plurality of physical processing cores; inter-core state discovery microcode in each core enabling the core to participate in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, sent to or received from other cores; wherein the inter-core state discovery microcode includes synchronization logic, provided to each core, synchronized instances of which are operable to be invoked on multiple cores for purposes of an inter-core state discovery process; wherein each native instance is operable both to invoke new instances of the synchronization logic on other cores, and to respond to any prior instance of the synchronization logic on another core that invoked the native instance; wherein the hierarchical coordination system groups cores into a plurality of domain levels, including at least; a primary-level domain of highest rank that includes all of the cores; and two or more secondary-level domains of equal next rank, immediately below the highest rank, that are constituents of and nested within the primary-level domain, each secondary-level group comprising respectively exclusive subgroups of the cores; for each multi-core domain level, a single core is designated as a master of that domain; each multi-core domain other than the lowest-level multi-core domains defines a kinship group consisting of master cores of constituent domains of the immediately next lower rank; each lowest-level multi-core domain defines a kinship group consisting of all of its cores; each core belongs to at least one kinship group; and each native instance of the synchronization logic is restricted from invoking new instances of the synchronization logic to cores not belonging to a native core kinship group. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A decentralized, microcode-implemented method of discovering states of a multi-core processor comprising a plurality of physical processing cores, the method comprising:
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inter-core state discovery microcode of at least two cores participating in a de-centralized inter-core state discovery process through signals, unmediated by any centralized non-core logic, exchanged by the cores; wherein the inter-core state discovery microcode includes synchronization logic, provided to each core, synchronized instances of which are operable to be invoked on multiple cores for purposes of an inter-core state discovery process; wherein each native instance is operable both to invoke new instances of the synchronization logic on other cores, and to respond to any prior instance of the synchronization logic on another core that invoked the native instance; wherein the hierarchical coordination system groups cores into a plurality of domain levels, including at least; a primary-level domain of highest rank that includes all of the cores; and two or more secondary-level domains of equal next rank, immediately below the highest rank, that are constituents of and nested within the primary-level domain, each secondary-level group comprising respectively exclusive subgroups of the cores; for each multi-core domain level, a single core is designated as a master of that domain; each multi-core domain other than the lowest-level multi-core domains defines a kinship group consisting of the master cores of constituent domains of the immediately next lower rank; each lowest-level multi-core domain defines a kinship group consisting of all of its cores; each core belongs to at least one kinship group; and each native instance of the synchronization logic is restricted from invoking new instances of the synchronization logic to cores not belonging to a native core kinship group. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification